[SOLVED] Post-Implementation Timing simulation for Ring oscillator

[osamaamin]

Hello,

I am trying to do a post-implementation timing simulation of a Ring Oscillator using Vivado 2014.1. But every time I got the error message:

FATAL_ERROR: Iteration limit 100000 is reached. Possible zero delay oscillation detected where simulation time can not advance.

Here is the code of ring oscillator:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity roPUF is
Port ( enable : in std_logic;
fout : inout STD_LOGIC);
end roPUF;

architecture ring_osc of roPUF is

constant NUM_INV : integer := 3;

signal int_net : STD_LOGIC_VECTOR (NUM_INV downto 0);
attribute dont_touch : string;
attribute dont_touch of int_net : signal is "true";
begin
int_net(0) <= enable and int_net(NUM_INV);
GEN_INV :
for I in 1 to NUM_INV generate
int_net(I) <= not int_net(I-1);
end generate GEN_INV;
fout <= int_net(NUM_INV);
end ring_osc;


I have tried to change to iteration limit to 100,000 using -maxdeltaid switch but still it won't work. Also I have checked the post-implementation schematic to make sure that my logic does not get trimmed by the tool.

 

[ads-ee]

Are you running the output "gate" level netlist with sdf?

 

[osamaamin]

Are you running the output "gate" level netlist with sdf?

The output netlist contains LUT based elements and the parameter $sdf_annotate to include the SDF file for the simulation.

 

[ads-ee]

Does the simulation report that it's annotating the design with the sdf? If so have you checked the sdf has the timing arcs for min/type/Max? And that you are spcifying that the similar use one that is populated.

 

[osamaamin]

Does the simulation report that it's annotating the design with the sdf? If so have you checked the sdf has the timing arcs for min/type/Max? And that you are spcifying that the similar use one that is populated.

I think so because it generates messages saying backannotation of sdf file successful. Yes the sdf file has timing arcs. I have set to use sdfmax in the simulation settings if that what you mean.

I think the problem is more with simulating the combinatorial loop in the ring oscillator, thats why the simulation fails to converge (although it should not happen after timing arcs have been specified). Because I tested a simple module for timing simulation and it was working.

 

[osamaamin]

I just tried simulating the same design with the ISE 14.4 and 14.7 and it is working correctly. This means that either there is some option that needs to be selected in Vivado to perform this type of simulation, or there is a bug in the tool.

 

[mrflibble]

Interesting. Did you find out yet if it is a Vivado bug, or if it is a case of not getting the constraints applied correctly?

 

[osamaamin]

I just found out that post synthesis and implementation timing simulations can not be done on VHDL files, even the testbench should also be in Verilog.

So to conclude, for post synthesis and implementation timing simulations using Vivado 2014.1, one should use the Verilog Design sources and testbench. The design sources can be in VHDL but for that the target language option in project settings should be selected as Verilog.

 

[K-J]

I just tried simulating the same design with the ISE 14.4 and 14.7 and it is working correctly. This means that either there is some option that needs to be selected in Vivado to perform this type of simulation, or there is a bug in the tool.

Is there an option for the minimum time increment? Maybe it is defaulting to 'ns' resolution and your delays are less than that so you would need to use 'ps'.

Kevin Jennings

 

[osamaamin]

It is automatically setting timestep of ps

 

[ads-ee]

I think I read something about Vivado not supporting Vital models at this time. I'll try to find the relevent doc, later today.

- - - Updated - - -

Just checked UG900 v2013.4 12/18/2013 and on pg 121 it states:

I still think I read somewhere that the Vivado simulator doesn't support the Vital models yet.

Same document on pg 109 shows the Tcl commands to run a timing simulation:


There is also a tip on pg 108 that states to do the write_verilog command before the write_sdf.

Regards

 

[osamaamin]

Yes you are right. Vivado does not has a simprim library (used in timing simulation) for VHDL.