Possibility on interfacing Altera Cyclone with PCI or PCI - E ?

[bianchi77]

Guys,

can I interface the I/O s of these boards :

EP4CE6E22C8N
**broken link removed**

EP4CE10F17C8N
https://www.ebay.com/itm/261188850625?ssPageName=STRK:MEWAX:IT&_trksid=p3984.m1438.l2649

Altera EP2C8Q208 FPGA / Nios II CORE
**broken link removed**

directly to PCI or PCI-E ? without transceiver ?
I wanna create adaptor PCB and connect it to one of those boards into PCI / PCI - e

thanks

 

[TrickyDicky]

Like ive said before, you dont need a tranceiver for PCI. But you dont have the correct connectors on that board for PCI. You cannot do PCIe for any of these boards.

I suggest you look at specific PCIe or PCI dev boards.

eg. http://www.altera.co.uk/products/devkits/altera/kit-aiigx-pcie.html

 

[bianchi77]

Like ive said before, you dont need a tranceiver for PCI. But you dont have the correct connectors on that board for PCI. You cannot do PCIe for any of these boards.

I suggest you look at specific PCIe or PCI dev boards.

eg. http://www.altera.co.uk/products/devkits/altera/kit-aiigx-pcie.html

Which connector do I need for PCI ?
because all off the I/O s are already on the header and I think I can use it for PCI connection....
do you have idea which I / O ? Bank 1 , bank 2...etc ?

thanks

- - - Updated - - -

Like ive said before, you dont need a tranceiver for PCI. But you dont have the correct connectors on that board for PCI. You cannot do PCIe for any of these boards.

I suggest you look at specific PCIe or PCI dev boards.

eg. http://www.altera.co.uk/products/devkits/altera/kit-aiigx-pcie.html

The board from altera is so expensive that's why I want to modify and create myself....

 

[TrickyDicky]

But those boards have everything you need, including the correct connectors and example designs to mess with and learn from. I think you'll have more trouble building your own.
The boards you listed are not PCI dev boards.

 

[FvM]

Cyclone FPGAs basically support 3V PCI without external transceivers. You'll most likely achieve better signal quality with external transceivers though. Interface to 5V PCI requires at least level translating bus switches.

 

[bianchi77]

Cyclone FPGAs basically support 3V PCI without external transceivers. You'll most likely achieve better signal quality with external transceivers though. Interface to 5V PCI requires at least level translating bus switches.

Do you have any examples for the board ? schematic ? FPGA with PCI interface schematic....
thanks

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Where can I get the schematic for the Altera cyclone fpgas with PCI interface ?
thanks a lot mate

 

[FvM]

There's an older Cyclone II development kit, it uses external transceivers as you can see from the photo. https://www.altera.com/products/devkits/altera/kit-pci-2c35.html

The schematics should and example software should be still available.

P.S.: I also remember a MAX II PCI kit. https://www.altera.com/products/devkits/altera/kit-maxii-1270.html
It's documentation is available for download. You can port the interface design to Cyclone.

 

[bianchi77]

There's an older Cyclone II development kit, it uses external transceivers as you can see from the photo. https://www.altera.com/products/devkits/altera/kit-pci-2c35.html

The schematics should and example software should be still available.

P.S.: I also remember a MAX II PCI kit. https://www.altera.com/products/devkits/altera/kit-maxii-1270.html


It's documentation is available for download. You can port the interface design to Cyclone.

do you mean this one ?
**broken link removed**

and the transceiver is :


Can I change the chip to :
EP2C5F256C7N or EP2C8Q208 and reduce some peripherals?

What's the minimum system needed, is it possible without DDR and Static RAM ? so I can reduce some I/O s and focusing on PCI ? how many I/Os do I need for PCI 32 bit ? 64 pins ?
Do you know where I can find 32 bit standard PCI connector for altium ?
thanks

 

[bianchi77]

can I use this one
**broken link removed** ?
for PCI interfacing ?
anyway how many pins do I need for PCI 32 bits 5V? is it compatible between PCI 32 bit 5V with cyclone II ?
Do you know where can I find the PCI 32 bits footprint for altium?
thanks

 

[Vanitar Nordic]

if it's a commercial project, you can buy PCI IP core for your specific purpose.

 

[bianchi77]

if it's a commercial project, you can buy PCI IP core for your specific purpose.

No it's not for commercial, it's for research and learning purpose....
any ideas ? thanks

 

[TrickyDicky]

http://www.altera.co.uk/products/ip/iup/pci/m-nwl-pci_core.html

 

[bianchi77]

Why did I get this :
Error: Too many I/O pins (52) assigned in I/O bank 1 - no more than 36 I/O pins are allowed in the I/O bank

There're 52 pins in bank 1 but I can't use them all....

- - - Updated - - -

http://www.altera.co.uk/products/ip/iup/pci/m-nwl-pci_core.html

they don't allow me to download....can I find it somewhere else ?

 

[FvM]

Why did I get this :
Error: Too many I/O pins (52) assigned in I/O bank 1 - no more than 36 I/O pins are allowed in the I/O bank

There're 52 pins in bank 1 but I can't use them all....

More exactly, the fitter error message tells about bidirectional I/Os ore something like this, I guess.

Pin placement constraints for particular FPGA families and I/O standards exist. They are usually documented and explained in detail in the the device manuals. In your design, the error might be brought up by omitting necessary attributes for the PCI bus like output enable groups.

The reason behind pin placement restrictions is the ground bounce effect. If too many outputs (or bidirectional pins) are driving out simultaneously, input signals in the same bank can be corrupted. By defining e.g. output enable grops, you tell the design compiler which bidirectional signals are not expected to interfer with each other.

 

[mrflibble]

There're 52 pins in bank 1 but I can't use them all....

Pins, or actual IO pins that are capable of the IO standard you want/need?

 

[bianchi77]

More exactly, the fitter error message tells about bidirectional I/Os ore something like this, I guess.

Pin placement constraints for particular FPGA families and I/O standards exist. They are usually documented and explained in detail in the the device manuals. In your design, the error might be brought up by omitting necessary attributes for the PCI bus like output enable groups.

The reason behind pin placement restrictions is the ground bounce effect. If too many outputs (or bidirectional pins) are driving out simultaneously, input signals in the same bank can be corrupted. By defining e.g. output enable grops, you tell the design compiler which bidirectional signals are not expected to interfer with each other.

Which pin should I update ?
Please see my attachment....thanks

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I tried to follow this documents page 12 Document : rn_pci_compiler_410.pdf
There's no error on "Analysis and ellaboration"
but when I start compilation, I got pin errors....

- - - Updated - - -

does anyone have PCI pin footprint for altium ? can I have the copy ? thanks

 

[FvM]

Looking at the EP2C8Q208 pinout file, I see 31 I/O and 4 input only pins. The problem is apparently about reading.

 

[mrflibble]

Yay! I suddenly feel both vindicated and mature. ^_^

Vindicated because I came to that same conclusion yesterday. And mature for not posting my somewhat sarcastic reply yesterday. So 1) please read the document you have already found and 2) if you had answered my earlier question (post #15) you would have found out what FvM pointed out. And 3) really try to read documentation, it's a handy skill.

 

[bianchi77]

Looking at the EP2C8Q208 pinout file, I see 31 I/O and 4 input only pins. The problem is apparently about reading.

if it's 35 pins only for one bank, i need 120 for PCI,
my problem is, I can't use bank 2 and bank 4 according to the manual.
Or I can override bank 2 and bank 4 for PCI interface,

For FvM
Thanks for replying and giving me a clue, I appreciate that, even it's the silliest question, I'm in the process of learning so I need to ask, it's better than I don't know and I don't have a clue...and it's getting worse if I don't wanna ask to someone else...
May I know what compiler do you use ? Quartus II ?

 

[FvM]

I can't use bank 2 and bank 4 according to the manual.

Why, exactly? Missing clamp diodes might be an issue, if you don't use any external level translators in a 3V PCI design.
I must confess, that I never attempted to implement a PCI bus with direct connected FPGA. Thus I'm possibly not aware of all detail problems.

May I know what compiler do you use ? Quartus II ?

Everyone is using Quartus with Altera FPGAs. Even if you are using a third party design compiler, you'll still rely on the Quartus tools to translate the netlist to hardware level. But I don't see a reasonable purpose to replace the Quartus compiler.