Positive edge-triggered flip flop does not work

Status
Not open for further replies.

mohamis288

Full Member level 3
Joined
Mar 1, 2022
Messages
164
Helped
0
Reputation
0
Reaction score
1
Trophy points
18
Activity points
1,235
I have implemented the Positive edge-triggered flip flop using the D-latch based diagram in cadence virtuoso.
For D-latch I have used the diagram in AckLP.png .
But it seems both edges are working.
What is the reason?



 

But it seems both edges are working. What is the reason?
How fast are the edges (rise and fall times)?
They must be less than the circuit propagation delay.
 
Last edited:
Solution
About 300us or lower
That's way too slow, and it causing your problem.
As I said, the rise/fall times need to be less than the circuit propagation delay, which is likely in the low ns region.
Use a Schmitt-trigger to reduce the signal transition times.
 

Question what "implemented" means. A DFF made of
verilog gates that have no delay, will fail because the
"hang time" is -too short- (0) and the DFFs need the
phase lag as "transient memory", to work. I have seen
this while building "structural verilog" views from transistor
level cell libraries. Delay properties or delay elements
had to be added.

The same may be true with too-slow-changing inputs
using SPICE modeled transistors but the question is
fundamental.
 
Reactions: FvM

remove first inv from the diagram, and remove the inv from 2nd dff , and try

[Moderator] Deleted unrelated advertising link
 
Last edited by a moderator:

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…