Positive and negative edge trigger flip flops

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surreyian

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edge trigger fip flop

Hello,

everytime we talk about positive edge trigger and negative edge trigger flip flop.
how do we design a postive edge trigger flip flop?
how do we design it to trigger at the 5th positive edge trigger.
what determines the umber of clocks it triggers at?
 

Re: edge trigger fip flop


hello,
what i know >>edge trigger FF can have many architectures , the most simple one
" for me" is using two oppositte latches "i.e. -ve latch then +ve latch >> +ve edge trig. , or +ve latch then -ve one >> -ve edge trigger" , about the # of edges u may use shift register (i.e. a series of registers with the edge u like "5 +ve in ur case" )
for the exact architectures "there r many" refer to any digital circuits book , i recommend RAbaey's >>dont remember its name .
bye.
 

Re: edge trigger fip flop

hello,

any recommendation on digital IC books, n where can i find them?
 

edge trigger fip flop

digital integrated circuits-a design perspective by rabaey is good.
 

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