Port mapping is giving me hell

[Hyro]

Having some real problems with some port mapping I know its probably something really easy, But I'm new to VHDL so I can't figure it out, would really appreciate the help.
__________________________________________________________________
Code:
entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(195 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
ABCDEF: out std_logic_vector(5 downto 0));
end MultiplexerX6;

architecture Structural of MultiplexerX6 is Error here

component Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(7 downto 0);
signal OutA_temp, OutB_temp, OutC_temp, OutD_temp, OutE_temp, OutF_temp : std_logic_vector(7 downto 0);

begin



A_temp <= DataStreams (31 downto 0);
B_temp <= DataStreams (64 downto 32);
C_temp <= DataStreams (97 downto 65);
D_temp <= DataStreams (130 downto 98 );
E_temp <= DataStreams (163 downto 131);
F_temp <= DataStreams (196 downto 164);

B1: Multiplexer32to8 port map(A_temp, SelectLine(1 DOWNTO 0), OutA_temp);
B2: Multiplexer32to8 port map(B_temp, SelectLine(3 DOWNTO 2), OutB_temp);
B3: Multiplexer32to8 port map(C_temp, SelectLine(5 DOWNTO 4), OutC_temp);
B4: Multiplexer32to8 port map(D_temp, SelectLine(7 DOWNTO 6), OutD_temp);
B5: Multiplexer32to8 port map(E_temp, SelectLine(9 DOWNTO 8 ), OutE_temp);
B6: Multiplexer32to8 port map(F_temp, SelectLine(11 DOWNTO 10), OutF_temp);

ABCDEF(0) <= OutA_temp; Error here
ABCDEF(1) <= OutB_temp; Error here
ABCDEF(2) <= OutC_temp; Error here
ABCDEF(3) <= OutD_temp; Error here
ABCDEF(4) <= OutE_temp; Error here
ABCDEF(5) <= OutF_temp; Error here

end Structural;
__________________________________________________________________
ErrorsMarked In Red)

HDLCompiler:841 Line 65. Type error near outa_temp ; expected type std_ulogic

HDLCompiler:841 Line 66. Type error near outb_temp ; expected type std_ulogic

HDLCompiler:841 Line 67. Type error near outc_temp ; expected type std_ulogic

HDLCompiler:841 Line 68. Type error near outd_temp ; expected type std_ulogic

HDLCompiler:841 Line 69. Type error near oute_temp ; expected type std_ulogic

HDLCompiler:841 Line 70. Type error near outf_temp ; expected type std_ulogic

HDLCompiler:854 Line 36. Unit structural ignored due to previous errors
VHDL file MultiplexerX6.vhd ignored due to errors
__________________________________________________________________

I would be really greatful if anyone could help. Thanks

 

[TrickyDicky]

you are trying to assign a 7 bit bus to a single bit of the output, hence the error.

Are you sure you dont mean:

ABCDEF(0) <= OutA_temp(0);
ABCDEF(1) <= OutB_temp(0);

 

[kirill]

OutX_temp is a vector, ABCDEF(0) is a scalar

 

[Hyro]

you are trying to assign a 7 bit bus to a single bit of the output, hence the error.

Are you sure you dont mean:

ABCDEF(0) <= OutA_temp(0);
ABCDEF(1) <= OutB_temp(0);

I see what you mean, but there are 8bit outputs for each ABCDEF (OUTPUT's). You see I'm trying to generate 6 Multiplexers that take 32bits as an input and release a 8bit output. By assigning ABCDEF(0) <= OutA_temp(0); means only 1 value in the vector is being allowed to output does it not?

---------- Post added at 19:47 ---------- Previous post was at 19:30 ----------

I think I see what you where getting at TrickyDicky so I made some changes to the code.

code:
_________________________________________________________________
entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(195 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
ABCDEF: out std_logic_vector(5 downto 0));
end MultiplexerX6;

architecture Structural of MultiplexerX6 is

component Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(31 downto 0);
signal OutA_temp, OutB_temp, OutC_temp, OutD_temp, OutE_temp, OutF_temp : std_logic_vector(7 downto 0);

begin



A_temp <= DataStreams (31 downto 0);
B_temp <= DataStreams (64 downto 32);
C_temp <= DataStreams (97 downto 65);
D_temp <= DataStreams (130 downto 98);
E_temp <= DataStreams (163 downto 131);
F_temp <= DataStreams (196 downto 164);

B1: Multiplexer32to8 port map(A_temp, SelectLine(1 DOWNTO 0), OutA_temp);
B2: Multiplexer32to8 port map(B_temp, SelectLine(3 DOWNTO 2), OutB_temp);
B3: Multiplexer32to8 port map(C_temp, SelectLine(5 DOWNTO 4), OutC_temp);
B4: Multiplexer32to8 port map(D_temp, SelectLine(7 DOWNTO 6), OutD_temp);
B5: Multiplexer32to8 port map(E_temp, SelectLine(9 DOWNTO 8), OutE_temp);
B6: Multiplexer32to8 port map(F_temp, SelectLine(11 DOWNTO 10), OutF_temp);

ABCDEF(0) <= OutA_temp(0) AND OutA_temp(1) AND OutA_temp(2)AND OutA_temp(3) AND OutA_temp(4) AND OutA_temp(5) AND OutA_temp(6) AND OutA_temp(7);
ABCDEF(1) <= OutB_temp(0) AND OutB_temp(1) AND OutB_temp(2)AND OutB_temp(3) AND OutB_temp(4) AND OutB_temp(5) AND OutB_temp(6) AND OutB_temp(7);
ABCDEF(2) <= OutC_temp(0) AND OutC_temp(1) AND OutC_temp(2)AND OutC_temp(3) AND OutC_temp(4) AND OutC_temp(5) AND OutC_temp(6) AND OutC_temp(7);
ABCDEF(3) <= OutD_temp(0) AND OutD_temp(1) AND OutD_temp(2)AND OutD_temp(3) AND OutD_temp(4) AND OutD_temp(5) AND OutD_temp(6) AND OutD_temp(7);
ABCDEF(4) <= OutE_temp(0) AND OutE_temp(1) AND OutE_temp(2)AND OutE_temp(3) AND OutE_temp(4) AND OutE_temp(5) AND OutE_temp(6) AND OutE_temp(7);
ABCDEF(5) <= OutF_temp(0) AND OutF_temp(1) AND OutF_temp(2)AND OutF_temp(3) AND OutF_temp(4) AND OutF_temp(5) AND OutF_temp(6) AND OutF_temp(7);

end Structural;
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The "Check Syntax" comes up completed Successfully, but weather are not it runs in simulation is an other thing!, will do that and hopefully get back to you soon.

 

[TrickyDicky]

what you've built isnt a mux, its just an anded version of the bits in all the out_temps. You need a select line and some different logic.

 

[Hyro]

what you've built isnt a mux, its just an anded version of the bits in all the out_temps. You need a select line and some different logic.

Your right! I've made some changes to the code but it looks like it not working again.

Code:
_________________________________________________________________
entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(191 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
ABCDEF: out std_logic_vector(5 downto 0));
end MultiplexerX6;

architecture Behavioral of MultiplexerX6 is --Error Here

component Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(31 downto 0);
signal Out_temp : std_logic_vector(5 downto 0);

begin

A_temp <= DataStreams (31 downto 0);
B_temp <= DataStreams (63 downto 32);
C_temp <= DataStreams (95 downto 64);
D_temp <= DataStreams (127 downto 96);
E_temp <= DataStreams (159 downto 128);
F_temp <= DataStreams (191 downto 160);

B1: Multiplexer32to8 port map(A_temp, SelectLine(1 DOWNTO 0), Out_temp(0)); --Error Here
B2: Multiplexer32to8 port map(B_temp, SelectLine(3 DOWNTO 2), Out_temp(1)); --Error Here
B3: Multiplexer32to8 port map(C_temp, SelectLine(5 DOWNTO 4), Out_temp(2)); --Error Here
B4: Multiplexer32to8 port map(D_temp, SelectLine(7 DOWNTO 6), Out_temp(3)); --Error Here
B5: Multiplexer32to8 port map(E_temp, SelectLine(9 DOWNTO 8), Out_temp(4)); --Error Here
B6: Multiplexer32to8 port map(F_temp, SelectLine(11 DOWNTO 10), Out_temp(5)); --Error Here

ABCDEF <= Out_temp;

end Behavioral;
________________________________________________________________
COMPONENT CODE:

entity Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end Multiplexer32to8;

architecture Behavioral of Multiplexer32to8 is

Signal A, B, C, D, Out_temp : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Wires used to create Input Array

Begin -- Main Body Begins

A <= DataStream (7 downto 0);
B <= DataStream (15 downto 8);
C <= DataStream (23 downto 16);
D <= DataStream (31 downto 24);

process (A, B, C, D, SelectLine)
Begin
Case SelectLine is
when "00" => out_temp <= A;
when "01" => out_temp <= B;
when "10" => out_temp <= C;
when "11" => out_temp <= D;
when others => out_temp <= "ZZZZZZZZ"; -- Return Default added
end case;
end process;

ABCDOut <= out_temp;

end Behavioral;
_________________________________________________________________
I keep getting the same errors:

ERROR:HDLCompiler:539 Indexed name is not a std_logic_vector
ERROR:HDLCompiler:539 Indexed name is not a std_logic_vector
ERROR:HDLCompiler:539 Indexed name is not a std_logic_vector
ERROR:HDLCompiler:539 Indexed name is not a std_logic_vector
ERROR:HDLCompiler:539 Indexed name is not a std_logic_vector
ERROR:HDLCompiler:539 Indexed name is not a std_logic_vector
ERROR:HDLCompiler:854 Unit behavioral ignored due to previous errors
VHDL file MultiplexerX6.vhd ignored due to errors

 

[TrickyDicky]

out_temp(0) is a single bit, you're trying to connect it to ABCDEF of the multiplexor that is 6 bits.

 

[Hyro]

I tried to fix this by creating more output pins as so:

entity MultiplexerX6 is
Port ( DataStreams : in std_logic_vector(191 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
AOut: out std_logic_vector(7 downto 0);
BOut: out std_logic_vector(7 downto 0);
COut: out std_logic_vector(7 downto 0);
DOut: out std_logic_vector(7 downto 0);
EOut: out std_logic_vector(7 downto 0);
FOut: out std_logic_vector(7 downto 0));
end MultiplexerX6;

architecture Structural of MultiplexerX6 is

component Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(31 downto 0);
signal OutA_temp, OutB_temp, OutC_temp, OutD_temp, OutE_temp, OutF_temp : std_logic_vector(7 downto 0);

begin

A_temp <= DataStreams (31 downto 0);
B_temp <= DataStreams (63 downto 32);
C_temp <= DataStreams (95 downto 64);
D_temp <= DataStreams (127 downto 96);
E_temp <= DataStreams (159 downto 128 );
F_temp <= DataStreams (191 downto 160);

B1: Multiplexer32to8 port map(A_temp, SelectLine(1 DOWNTO 0), OutA_temp);
B2: Multiplexer32to8 port map(B_temp, SelectLine(3 DOWNTO 2), OutB_temp);
B3: Multiplexer32to8 port map(C_temp, SelectLine(5 DOWNTO 4), OutC_temp);
B4: Multiplexer32to8 port map(D_temp, SelectLine(7 DOWNTO 6), OutD_temp);
B5: Multiplexer32to8 port map(E_temp, SelectLine(9 DOWNTO 8 ), OutE_temp);
B6: Multiplexer32to8 port map(F_temp, SelectLine(11 DOWNTO 10), OutF_temp);

AOut <= OutA_temp;
BOut <= OutB_temp;
COut <= OutC_temp;
DOut <= OutD_temp;
EOut <= OutE_temp;
FOut <= OutF_temp;

end Structural;
_______________________________________________________________________________________________
It works in a syntax check, but not in simulation
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I don't know where to go from here, does anyone know how to fix this? Where did I go wrong?

Also This VHDL Module doesn't show up in the Implementation Source window, and can only be seen in the Behavioral Simulation window, so not allowing me to run simulation.

 

[vipinlal]

in xilinx software window, go to 'files'. Right click and change the association to "all". then the file will be displayed in implementation source window too.

 

[Aritra17]

your code does give a output
but i don't think that is what you want
if you are doing this coding in xilinx then try to correct the warnings
your code has 56 warnings


and by the way can anyone tell me what is a ' black box module' ??
your code warning shows all the port map connections as ' black box module'
what is that?

---------- Post added at 04:01 ---------- Previous post was at 03:58 ----------

in xilinx software window, go to 'files'. Right click and change the association to "all". then the file will be displayed in implementation source window too.

vipinlal can you explain what are you trying to say
i have tried to do as per you have said
but there is nothing named as association

 

[vipinlal]

There is an option named "set view association to" when you right click on the file under files tab.

He hasnt shared the Multiplexer32to8 code here. Thats why you got the blackbox warning/error.

 

[lucbra]

There is an option named "set view association to" when you right click on the file under files tab.

He hasnt shared the Multiplexer32to8 code here. Thats why you got the blackbox warning/error.

Yes he did, some posts before ...

---------- Post added at 15:44 ---------- Previous post was at 15:43 ----------

I advise the OP to start with a simple mux and then extend to a bus structure

 

[Aritra17]

no he hasn't mentioned the multiplexer32to8 code here
he has just mentioned the component
thanks vipinlal for the black box concept
and hyro i would suggest you to code simply


your code:

AOut <= OutA_temp;
BOut <= OutB_temp;
COut <= OutC_temp;
DOut <= OutD_temp;
EOut <= OutE_temp;
FOut <= OutF_temp;


this part is unnecessary

you could have done directly

B1: Multiplexer32to8 port map(A_temp, SelectLine(1 DOWNTO 0), AOut);


like this

make it simple to understand

and if your component is working fine then this code should also work great

 

[lucbra]

See post #6

entity Multiplexer32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end Multiplexer32to8;

architecture Behavioral of Multiplexer32to8 is

Signal A, B, C, D, Out_temp : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Wires used to create Input Array

Begin -- Main Body Begins

A <= DataStream (7 downto 0);
B <= DataStream (15 downto ;
C <= DataStream (23 downto 16);
D <= DataStream (31 downto 24);

process (A, B, C, D, SelectLine)
Begin
Case SelectLine is
when "00" => out_temp <= A;
when "01" => out_temp <= B;
when "10" => out_temp <= C;
when "11" => out_temp <= D;
when others => out_temp <= "ZZZZZZZZ"; -- Return Default added
end case;
end process;

ABCDOut <= out_temp;

end Behavioral;

 

[Hyro]

Thanks guys to all the replies. I did manage to get it working, that is that the code does work I ran the code through a Altera software pack rather than the xilinx 10.1 package I was using, the code simulates perfectly in it.

I'd like to just say thanks to everyone for helping.

Also vipinlal you had a good point about the association options it was a good tip, so I went back to using the Xilinx 10.1 to see if changing the association to all on the file, however for some unknown reason that still wouldn't work lol. But thats ok I know the code works does exactly what I want it to. Allowing me to continue on with the rest of the component files i'm writing up thanks again.

PS
Just encase your all wondering what the finished bit of code looks like here it is:

entity MUX32to8X6 is
Port ( DataStreams : in std_logic_vector(191 downto 0);
SelectLine : in std_logic_vector(11 downto 0);
AOut: out std_logic_vector(7 downto 0);
BOut: out std_logic_vector(7 downto 0);
COut: out std_logic_vector(7 downto 0);
DOut: out std_logic_vector(7 downto 0);
EOut: out std_logic_vector(7 downto 0);
FOut: out std_logic_vector(7 downto 0));
end MUX32to8X6;

architecture Behavioral of MUX32to8X6 is

component MUX32to8 is
Port ( DataStream : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SelectLine : in STD_LOGIC_VECTOR(1 DOWNTO 0);
ABCDOut : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end component;

signal A_temp, B_temp, C_temp, D_temp, E_temp, F_temp : std_logic_vector(31 downto 0);

begin


A_temp <= DataStreams (31 downto 0);
B_temp <= DataStreams (63 downto 32);
C_temp <= DataStreams (95 downto 64);
D_temp <= DataStreams (127 downto 96);
E_temp <= DataStreams (159 downto 128);
F_temp <= DataStreams (191 downto 160);

B1: MUX32to8 port map(DataStream => A_temp, SelectLine => SelectLine(1 DOWNTO 0), ABCDOut => AOut);
B2: MUX32to8 port map(DataStream => B_temp, SelectLine => SelectLine(3 DOWNTO 2), ABCDOut => BOut);
B3: MUX32to8 port map(DataStream => C_temp, SelectLine => SelectLine(5 DOWNTO 4), ABCDOut => COut);
B4: MUX32to8 port map(DataStream => D_temp, SelectLine => SelectLine(7 DOWNTO 6), ABCDOut => DOut);
B5: MUX32to8 port map(DataStream => E_temp, SelectLine => SelectLine(9 DOWNTO 8), ABCDOut => EOut);
B6: MUX32to8 port map(DataStream => F_temp, SelectLine => SelectLine(11 DOWNTO 10), ABCDOut => FOut);


end Behavioral;