Hello everybody!
i'm here again because i'm very lazy and i want to simplify my life
i'm writing the hdl code of a kogge stone radix2 (dense) at 8 bit, and i was wondering if is possible to define signals and port map in a loop, to avoid to write a lot of code, and also to make the implementation indipendet form the number of bits!
look into for-generate blocks in VHDL, or generate blocks with genvar's in Verilog. note that VHDL does things in a logical manner, while Verilog hacked generates into the language. both can have nested generate blocks in some manner, but Verilog defines all of the genvar's outside of a single block. VHDL just allows generate blocks to be contained within other generate blocks.
in VHDL, you can define signals an constants for internal use as well. processes can also be inside a generate.
Keep in mind that, for FPGA's, fancy adders almost never provide a benefit over the default that you get from just using a+b. This is because the FPGA fabric has very fast routing in place for them, while the fancy adders must use mostly general purpose routing.
Hello, your nightmare is here again!
i read something about the generate stantment in vhdl, and i tried to modify the ripple carry adder attached to this Thread
. I added the carry in at the 8 bit adder, and modify the structure in this way
Code:
signal carry:std_logic_vector(7 downto 0);
begin
carry(0)<='0';
c: for i IN 0 to 6 generate
c1to6: fa port map (a8(i), b8(i), carry(i), s8(0), carry(i+1));
end generate;
c7: fa port map (a8(7), b8(7), carry(7), s8(7), cout);