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port mapping and signals in a loop

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tj.diego

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Hello everybody!
i'm here again because i'm very lazy and i want to simplify my life :cool:
i'm writing the hdl code of a kogge stone radix2 (dense) at 8 bit, and i was wondering if is possible to define signals and port map in a loop, to avoid to write a lot of code, and also to make the implementation indipendet form the number of bits!

Thanks a lot in advance

ps i attach the code and the figure i'm using!kogge.pngView attachment koggestone.txt
 

permute

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look into for-generate blocks in VHDL, or generate blocks with genvar's in Verilog. note that VHDL does things in a logical manner, while Verilog hacked generates into the language. both can have nested generate blocks in some manner, but Verilog defines all of the genvar's outside of a single block. VHDL just allows generate blocks to be contained within other generate blocks.

in VHDL, you can define signals an constants for internal use as well. processes can also be inside a generate.

Keep in mind that, for FPGA's, fancy adders almost never provide a benefit over the default that you get from just using a+b. This is because the FPGA fabric has very fast routing in place for them, while the fancy adders must use mostly general purpose routing.
 

tj.diego

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Hello, your nightmare is here again! :D
i read something about the generate stantment in vhdl, and i tried to modify the ripple carry adder attached to this Thread
. I added the carry in at the 8 bit adder, and modify the structure in this way

Code:
signal carry:std_logic_vector(7 downto 0);
begin
carry(0)<='0';
c: for i IN 0 to 6 generate
  c1to6: fa port map (a8(i), b8(i), carry(i), s8(0), carry(i+1));
end generate;

c7: fa port map (a8(7), b8(7), carry(7), s8(7), cout);
but the sum is metastable!

advice?!

thanks a lot in advance!!!
 

mrflibble

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If it is metastable maybe you need to register it?
 

tj.diego

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i really hope that a ripple carry adder doesn't need to be registrered!
btw this is the result of the simulation!
Schermata.png
 

mrflibble

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i really hope that a ripple carry adder doesn't need to be registrered!
btw this is the result of the simulation!
View attachment 55602
That's not metastable. That's in all probability wrongly generated + setup/hold violations.

notice how the first bit is sometimes an X and sometimes a 0. The X is probably setup/hold violation.

To see the difference ... how about slowing down the clock by a factor of 100 and see if there is a different result. That should change some X's.
 

TrickyDicky

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you connect all of the sum from the generate loop to s(0) rather than s(i), hence your problem.
 

tj.diego

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thanks TrickyDicky, your answer was the solution! :)
 

mrflibble

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in all probability wrongly generated. check. :p
 

tj.diego

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yes you was right too, but his answer was more helpful! :)
 

mrflibble

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I know. I was just too lazy to go through it at that point in time. ;) Besides, I am not that great at vhdl... Glad you got it working. :)
 

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