Depends how good you want the dummy to be, and what
aspects of process lithography stand to affect device
match.
If you don't know, in detail (and even "inside foundry" guys
rarely do) then "like for like" is the only sound approach.
You may get some poly geometry uniformity out of a
poly-only "dummy" (presuming you make its relation to the
first real FET, same as FET1:FET2, FET2:FET3, ...). But
what about the active area litho, STI strain effects and
so on? Are "half measures" even worth taking? Who knows?
Not sure why you think dummies add meaningful parasitic
effects. Yes, they all have parasitic elements. But if you
tie the gate and outboard S/D region to body then the
only parasitic that does anything is the Cbs and maybe the
second Cgd (or Cgs) capacitance of the dummy gate to
the end S/D region - which only makes the end FET more
like the center FET. OK, you can reduce the parasitic loading.
So what? Model it and decide whether it matters enough to
be worth chasing.