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Poly dummy instead of poly transistor

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Junus2012

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Hi every one

is it possible to use only poly at the end of my matched transistor array instead of using dummy trsansistor. I believe this will reduce the parasatics induced by the dummy transistor.

Below is the image from Jakob book, I think that the same poly to connect the gates is serving as a dummy layer for the functional transistors

layout.png
 

dick_freebird

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Depends how good you want the dummy to be, and what
aspects of process lithography stand to affect device
match.

If you don't know, in detail (and even "inside foundry" guys
rarely do) then "like for like" is the only sound approach.

You may get some poly geometry uniformity out of a
poly-only "dummy" (presuming you make its relation to the
first real FET, same as FET1:FET2, FET2:FET3, ...). But
what about the active area litho, STI strain effects and
so on? Are "half measures" even worth taking? Who knows?

Not sure why you think dummies add meaningful parasitic
effects. Yes, they all have parasitic elements. But if you
tie the gate and outboard S/D region to body then the
only parasitic that does anything is the Cbs and maybe the
second Cgd (or Cgs) capacitance of the dummy gate to
the end S/D region - which only makes the end FET more
like the center FET. OK, you can reduce the parasitic loading.
So what? Model it and decide whether it matters enough to
be worth chasing.
 

Junus2012

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Dear freeBird,

Thank you very much for your help,

according to your explanation and Suta, I will pay the effort of using the dummy transistors. I am using these connection as shown below

New Doc 58.jpg

New Doc 60 1.jpg

Thank you once again
 

sutapanaki

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It matters a lot what kind of technology process we are talking about. I think for newer processes with STI etc, dummies are a better approach compared to just a poly dummy. For older technologies, say 500um and above, with LOCOS type of isolations probably poly stripes can do a decent job. I remember when I worked on 1um process we used to use poly dummies. But nowadays it is always device dummies.
 

Junus2012

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Thank you Suta,

I am using the 0.35 uM classical technology. it uses the FOX for isolation.

I have a question please, I used the poly (not the case of my current work as I already used the dummy transistor), it means I can only draw a bar of poly and give it a contact to VDD or to GND according to the type of the matched transistor, but LVS will not complain that he found something different from schematic or it is just a shorted wire then no problem.

Thank you once again
 

sutapanaki

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LVS shouldn't complain since this is not a device. However, from the picture in your first post, those poly dummies are connected same as gates of transistors, of course at the expense of more gate capacitance.
 
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