Feb 21, 2003 #1 T tahiti Junior Member level 2 Joined Jan 23, 2003 Messages 24 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,283 Activity points 262 Please state and describe your opinion... tahiti
Mar 6, 2003 #2 T tahiti Junior Member level 2 Joined Jan 23, 2003 Messages 24 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,283 Activity points 262 bah... only 4 votes and verification is supposed to be 70% (or even more to some studies) of design effort of modern SoC systems... well, it seems that we don't have many verification people around yet... tahiti
bah... only 4 votes and verification is supposed to be 70% (or even more to some studies) of design effort of modern SoC systems... well, it seems that we don't have many verification people around yet... tahiti
Mar 6, 2003 #3 T tlihu Full Member level 6 Joined Jan 2, 2002 Messages 335 Helped 19 Reputation 42 Reaction score 13 Trophy points 1,298 Activity points 2,259 I only heard of Verilog/VHDL.
Mar 13, 2003 #4 E eda_wiz Advanced Member level 2 Joined Nov 7, 2001 Messages 653 Helped 58 Reputation 116 Reaction score 29 Trophy points 1,308 Activity points 6,195 hi, I am sorry. But I dont know what is an HVL . can Anyone please tellme that tnx
Mar 13, 2003 #5 K kinysh Member level 3 Joined Jul 16, 2002 Messages 65 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 509 well, seems most of us still use verilog/vhdl to do the verification. acutally I think the verification is limitted to the cpu speed. so we can not verify all the corner case on verification because of speed. to cover all the corner case, random test is really need, and long time running is also important. so instead, I prefer to use fpga to verify the whole design for full coverage. the speed is 100:1. bests kinysh
well, seems most of us still use verilog/vhdl to do the verification. acutally I think the verification is limitted to the cpu speed. so we can not verify all the corner case on verification because of speed. to cover all the corner case, random test is really need, and long time running is also important. so instead, I prefer to use fpga to verify the whole design for full coverage. the speed is 100:1. bests kinysh
Mar 13, 2003 #6 K kinysh Member level 3 Joined Jul 16, 2002 Messages 65 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 509 ha, seems I am the first one post some opinion. cheer!!1 :wink: :wink: :wink:
Mar 13, 2003 #7 J joe2moon Full Member level 5 Joined Apr 19, 2002 Messages 280 Helped 19 Reputation 38 Reaction score 7 Trophy points 1,298 Location MOON Activity points 3,717 HVL Just like HDL stands for "Hardware Description Language", such as Verilog and VHDL. HVL is the abbreviation of "Hardware Verification Language", such as OpenVera and SystemVerilog. Maybe take a look at the following link: (0rg -> org) h**p://www.hdlcon.0rg/index.html
HVL Just like HDL stands for "Hardware Description Language", such as Verilog and VHDL. HVL is the abbreviation of "Hardware Verification Language", such as OpenVera and SystemVerilog. Maybe take a look at the following link: (0rg -> org) h**p://www.hdlcon.0rg/index.html