Plz help me with these DRC errors

[lokesh garg]

DRC error

i mdae layout of inverter in UMC 90 nm technology.. whern i run DRC it's showing many errors like ..
metal 1 coverage must be larger than 20% over lacal 100um*100um area step 50um
this error is showing upto metal 11.. there is one another error is coming... Die corner rule 1, ME! must draw with 135 angle.... plz help me... its very urgent for me..... plzzzzzzzzzzz

 

[deepak242003]

Re: DRC error

i mdae layout of inverter in UMC 90 nm technology.. whern i run DRC it's showing many errors like ..
metal 1 coverage must be larger than 20% over lacal 100um*100um area step 50um

It is M1 density error. Your need to fill more M1. (which i doubt in inverter) probably your instance layer is not at proper place and size.

this error is showing upto metal 11..

you can ignore this error after metal1 bcause ( I assume) you are using only upto metal 1.

there is one another error is coming... Die corner rule 1, ME! must draw with 135 angle.... plz help me... its very urgent for me..... plzzzzzzzzzzz

I believe only orthogonal connection is allowed in umc except in chip corners.you might have used non orthogonal connection sumwhere.check.

 

[lokesh garg]

thanks for ur reply.....
but how will i fill more metal 1 in my layout.. plz tell me

Added after 4 minutes:

if u have some already made layout in UMC 90nm technology file... plzzzzzzz give me layout of that ckt.....plzzzzzzzzz

 

[oermens]

unless you have designed a revolutionary inverter, i doubt you are submitting this for fabrication. then why bother worrying about density rules? same for esd, latchup, guardring, seal ring, etc. you should be able to turn these checks off in your drc checker.

 

[lokesh garg]

i m not submitting this for fabrication..... canu tell me how will i turn off these density options ion DRC checker...

 

[maqadar]

I think your inverter does not cover as much as 100u X 100um area.
Now draw a prboundary with 100u X 100um rectangle. Fill this empty(non inverter)area with the type of layer needed. Better to fill the empty area with small rectangles. If you use a bigger width metal you will have to slot this metal width.

As far as the die corner rule is concerned, it can cleared only at the chip level when the inverter is placed at the top level with the pads........

Hope this helps.....

 

[psrujan]

Switch off Density-check and/or Top-level checks by using switches.. If you don't how how to use switches... there is nothing to be worried about these errors at sub-cell level... you can ignore these errors for an single inverter design for sure..

 

[npardeepsain]

you can ignore any density errors at cell level..( I mean if tile size is very big than gds size ) .. you can just leave those density violation. To get to know how exactly your design fail the density violation,at higher level you need to place the cell stacked to each other such a way that it can cover the window size specified in rule and then run the DRC, if you think still density violation reports then you need to redesign the structure...

Generally speaking ignore those density violations.. or ask your DRC developer to provide the switch in the DRC rule file.

Also one advise I will give here, do not copy the rule description in this form. This is confidential data and you should not be copying this anywhere..