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Plz help me to simulate CMOS Source-degeneration Gm-cell with NIC circuit in Virtuos

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babu1sharath

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This Source degeneration Gm-cell with negative-impedance-compensation(NIC) technique is used to
design loop-filter for 2nd order Sigma Delta ADC. I dont know what are the parameters/specifications needed for the design of the ADC. Also i need input parameter values like Vsin, Vref, Vss for this Source-degeneration Gm-cell. I am using Cadence 180nm. So Any one having idea plz help(i uploaded both circuit and cadence cell view)
 

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