plz help me solve these erors in xilinx project

[hari_lhr]

ngdbuild:604 - logical block

plz help as its urgent.. i find these eror when i double click on "implement design" tab...............i am using xilinx ISe 7.i


NgdBuild:604 - logical block 'SM' with type 'TxStateMachine' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'TxStateMachine' is not supported
in target 'aspartan3'.
ERROR:NgdBuild:604 - logical block 'CRCCnt' with type 'CRCCounter' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'CRCCounter' is not supported in
target 'aspartan3'.
ERROR:NgdBuild:604 - logical block 'RA' with type 'RegArray' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'RegArray' is not supported in
target 'aspartan3'.
ERROR:NgdBuild:604 - logical block 'DM' with type 'DataMux' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'DataMux' is not supported in
target 'aspartan3'.
ERROR:NgdBuild:604 - logical block 'CRC51' with type 'CRC5' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'CRC5' is not supported in target
'aspartan3'.
ERROR:NgdBuild:604 - logical block 'CRC161' with type 'CRC16' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'CRC16' is not supported in target
'aspartan3'.
ERROR:NgdBuild:604 - logical block 'DLC1' with type 'DLC' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'DLC' is not supported in target
'aspartan3'.
ERROR:NgdBuild:604 - logical block 'FI' with type 'fifo_32_32' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'fifo_32_32' is not supported in
target 'aspartan3'.
ERROR:NgdBuild:604 - logical block 'Bybi' with type 'BytetoBit' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'BytetoBit' is not supported in
target 'aspartan3'.
ERROR:NgdBuild:604 - logical block 'DWB' with type 'dwtobyte' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'dwtobyte' is not supported in
target 'aspartan3'.
ERROR:NgdBuild:604 - logical block 'NRZ' with type 'NRZI' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'NRZI' is not supported in target
'aspartan3'.

NGDBUILD Design Results Summary:
Number of errors: 11
Number of warnings: 0


One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "txtopmodule.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.

 

[mahditooba]

ngdbuild 604 logical block

first time clean your project.
if not resolved check pin assignment and package

 

[Aastik]

error ngdbuild:604

Hi,

The primary reason for this error is that your project is missing EDIF files. During synthesis, the synthesis tool has probably created black_boxs for some of the modules. Now during implementation the tool needs all the EDIFs of the modules which were created black boxes. What you need to do is go through your synthesis report and see what modules were created black boxes and why. you may probably have to look at your RTL to find out why black boxes were created.

I hope this helps.

Regards.

 

[hari_lhr]

pin name misspelling error

i am new to xilinx so plz tell me how to find why a black box is created and how to get EDIF

 

[Aastik]

could not be resolved xilinx

Hi,

Which synthesis tool are you using? Have you written the RTL yourself?

If you are using Synplify, just search "unbound" or "black" keyword in the syntesis log file. Read the warnings having these keywords. It will give you some idea.

Regards.

 

[hari_lhr]

logical block with type could not be resolved

Hi,

Which synthesis tool are you using? Have you written the RTL yourself?

If you are using Synplify, just search "unbound" or "black" keyword in the syntesis log file. Read the warnings having these keywords. It will give you some idea.

Regards.

can u help me out if i post the code for th USB transmitter,in which i am finding these problem..

 

[Aastik]

unbound component synplify why

Please do it.

I will try to have a look at it.

Regards.

 

[hari_lhr]

process translate did not complete ise

Please do it.

I will try to have a look at it.

Regards.

i am attaching the code..plz tell step by step how to do it in xilinx....plz don't use very high technical language while explaining

u can find the code at

 

[Aastik]

error:ngdbuild:604

Hari,

The code which you have given is not complete in the sense that there's no definitions for all the components declared.

In a simpler way, you should have RTL code for all the components used. For example you are using "RegArray", "DataMux" etc. Your project should also have RTL for "RegArray", "DataMux" etc.

I hope you understood what I tried to say.

 

[hari_lhr]

+synplify +ngdbuild:604

Hari,

The code which you have given is not complete in the sense that there's no definitions for all the components declared.

In a simpler way, you should have RTL code for all the components used. For example you are using "RegArray", "DataMux" etc. Your project should also have RTL for "RegArray", "DataMux" etc.

I hope you understood what I tried to say.

hi
may i tell u wht i have done...
1. i created entity and architecture for all the components i mentioned
2. grouped into components in "txtopmodule"

then wrote the rest..
i dont undrstand how to work on the test bench..
i just got the code from my frnd

try to comment

 

[hari_lhr]

xilinx name could not be resolved

Hari,

The code which you have given is not complete in the sense that there's no definitions for all the components declared.

In a simpler way, you should have RTL code for all the components used. For example you are using "RegArray", "DataMux" etc. Your project should also have RTL for "RegArray", "DataMux" etc.

I hope you understood what I tried to say.

All the components like "RegArray", "DataMux" etc have RTL
but in the end the implementation fails bcoz of some error..i mentioned earlier