plz help me in this verilog code

module readmemh_demo
(
output reg lclk,
output reg [31:0] pixels
);

reg [31:0] Mem [0:20];

initial $readmemh("pixels.txt",Mem);

reg[7:0] k;
reg[7:0] i;
initial begin
$dumpfile("file.vcd");
$dumpvars;
end
initial begin
lclk = 0;
k = 0;
pixels = 32'b0;
end
initial fork
forever lclk = #5 ~lclk;
join
always @(posedge lclk)begin
pixels = Mem[k];
k = k+1;
#100 $finish;
end
endmodule

here actually i am reaing a text file which is having only the pixels......now i have to send these pixels word by word to the next module......but here only one data is given as output to the next module....the k is not incrementing for every posedge lclk....how i can do this?plzzzz some one help me to solve this....

You cannot have this -" #100 $finish;" in an always block(read up on "always blocks" in verilog). Move that "$finish" out of the always block if you want the $finish statement. Also when you say word do you mean 4bytes? Right now your code outputs 8 bits at a time.