sandeshrai
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 00:13:44 03/31/2012 -- Design Name: -- Module Name: visitor_counter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity visitor_counter is Port ( --sys_clk : in STD_LOGIC; sensor_1 : in STD_LOGIC :='0'; sensor_2 : in STD_LOGIC :='0'; rst : in STD_LOGIC; -- H : out STD_LOGIC_vector(3 downto 0); T : out STD_LOGIC_vector(3 downto 0); O : out STD_LOGIC_vector(3 downto 0)); end visitor_counter; architecture Behavioral of visitor_counter is -- signal clk1 : std_logic; -- signal visitor_count : integer :=0; signal ones, tens : integer :=0; -- signal hundreds : integer :=0; -- COMPONENT clk_div -- PORT( -- sys_clk : IN std_logic; -- q : OUT std_logic -- ); -- END COMPONENT; begin -- Inst_clk_div: clk_div PORT MAP( -- sys_clk => sys_clk, -- q => clk1 -- ); process (rst, sensor_1, sensor_2) begin if rst='1' then ones<= 0; tens<= 0; -- hundreds<= 0; elsif rising_edge(sensor_1) and rising_edge(sensor_2) then ones<=ones; tens<=tens; elsif rising_edge(sensor_1) then ones <= ones + 1 ; -- if ones>9 then -- tens<=tens+1; -- ones<=0; -- if tens>9 then -- hundreds<=hundreds+1; -- tens<=0; -- end if; -- end if; elsif rising_edge(sensor_2) then ones <= ones - 1 ; -- if ones<0 then -- tens<=tens-1; -- ones<=9; -- if tens<0 then -- hundreds<=hundreds-1; -- tens<=9; -- end if; -- end if; else ones <= ones; tens <= tens; --hundreds <= hundreds; end if; --case hundreds is --when 0 => -- H<="0000"; --when 1 => -- H<="0001"; --when 2 => -- H<="0010"; --when 3 => -- H<="0011"; --when 4 => -- H<="0100"; --when 5 => -- H<="0101"; --when 6 => -- H<="0110"; --when 7 => -- H<="0111"; --when 8 => -- H<="1000"; --when others => -- H<="1001"; -- hundreds <=0; --end case; case tens is when 0 => T<="0000"; when 1 => T<="0001"; when 2 => T<="0010"; when 3 => T<="0011"; when 4 => T<="0100"; when 5 => T<="0101"; when 6 => T<="0110"; when 7 => T<="0111"; when 8 => T<="1000"; when 9 => O<="1001"; when 10 => -- hundreds<=hundreds+1; tens <=0; when others => -- hundreds<=hundreds-1; tens <=9; end case; case ones is when 0 => O<="0000"; when 1 => O<="0001"; when 2 => O<="0010"; when 3 => O<="0011"; when 4 => O<="0100"; when 5 => O<="0101"; when 6 => O<="0110"; when 7 => O<="0111"; when 8 => O<="1000"; when 9 => O<="1001"; when 10 => tens<=tens+1; ones <=0; when others => tens<=tens-1; ones <=9; end case; end process; end Behavioral;
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