Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 00:13:44 03/31/2012 -- Design Name: -- Module Name: visitor_counter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity visitor_counter is Port ( --sys_clk : in STD_LOGIC; sensor_1 : in STD_LOGIC :='0'; sensor_2 : in STD_LOGIC :='0'; rst : in STD_LOGIC; -- H : out STD_LOGIC_vector(3 downto 0); T : out STD_LOGIC_vector(3 downto 0); O : out STD_LOGIC_vector(3 downto 0)); end visitor_counter; architecture Behavioral of visitor_counter is -- signal clk1 : std_logic; -- signal visitor_count : integer :=0; signal ones, tens : integer :=0; -- signal hundreds : integer :=0; -- COMPONENT clk_div -- PORT( -- sys_clk : IN std_logic; -- q : OUT std_logic -- ); -- END COMPONENT; begin -- Inst_clk_div: clk_div PORT MAP( -- sys_clk => sys_clk, -- q => clk1 -- ); process (rst, sensor_1, sensor_2) begin if rst='1' then ones<= 0; tens<= 0; -- hundreds<= 0; elsif rising_edge(sensor_1) and rising_edge(sensor_2) then ones<=ones; tens<=tens; elsif rising_edge(sensor_1) then ones <= ones + 1 ; -- if ones>9 then -- tens<=tens+1; -- ones<=0; -- if tens>9 then -- hundreds<=hundreds+1; -- tens<=0; -- end if; -- end if; elsif rising_edge(sensor_2) then ones <= ones - 1 ; -- if ones<0 then -- tens<=tens-1; -- ones<=9; -- if tens<0 then -- hundreds<=hundreds-1; -- tens<=9; -- end if; -- end if; else ones <= ones; tens <= tens; --hundreds <= hundreds; end if; --case hundreds is --when 0 => -- H<="0000"; --when 1 => -- H<="0001"; --when 2 => -- H<="0010"; --when 3 => -- H<="0011"; --when 4 => -- H<="0100"; --when 5 => -- H<="0101"; --when 6 => -- H<="0110"; --when 7 => -- H<="0111"; --when 8 => -- H<="1000"; --when others => -- H<="1001"; -- hundreds <=0; --end case; case tens is when 0 => T<="0000"; when 1 => T<="0001"; when 2 => T<="0010"; when 3 => T<="0011"; when 4 => T<="0100"; when 5 => T<="0101"; when 6 => T<="0110"; when 7 => T<="0111"; when 8 => T<="1000"; when 9 => O<="1001"; when 10 => -- hundreds<=hundreds+1; tens <=0; when others => -- hundreds<=hundreds-1; tens <=9; end case; case ones is when 0 => O<="0000"; when 1 => O<="0001"; when 2 => O<="0010"; when 3 => O<="0011"; when 4 => O<="0100"; when 5 => O<="0101"; when 6 => O<="0110"; when 7 => O<="0111"; when 8 => O<="1000"; when 9 => O<="1001"; when 10 => tens<=tens+1; ones <=0; when others => tens<=tens-1; ones <=9; end case; end process; end Behavioral;
elsif rising_edge(sensor_1) and rising_edge(sensor_2) then
ones<=ones;
tens<=tens;
elsif rising_edge(sensor_1) then
shaiko.... i just want to make an input controlled BCD counter... not a clock controlled.... it should increment when i give sensor_1 and decrement when i give sensor_2.......Please explain what you want your code to do...
You should strongly consider using a clock and making your logic synchronous.
I.E evaluate all data signal under
if rising_edge ( clock ) then
as opposed to:
if rising_edge ( not_a_clock_signal ) then
Problem is here...
You mustCode:elsif rising_edge(sensor_1) and rising_edge(sensor_2) then ones<=ones; tens<=tens; elsif rising_edge(sensor_1) then
- Pick one (and only one) signal to have for the 'rising_edge'
- You must use one (and only one) 'rising_edge' function in an 'elsif' branch (and no, you cannot use 'rising' and 'falling' edge either...only one of them)
- You must have one (and only one) 'elsif' branch
Then you'll have a synchronous description
Kevin Jennings
That's because you didn't do as I saidthanks for the help, I tried using only one rising_edge function with one elsif as You asked me to but the problem still persists....
Different than what? You say you changed your code, but you didn't post it.I would we grateful to you, if you suggest me some different logic for my requirement....
If you use the 'rising_edge' function of 'sensor_1' and 'sensor_2' then you will never succeed...because that violates the rules that I gave you before. Here is something for you to ponder that will help:I need to make an input controlled BCD counter.... on rising edge of sensor_1 it should increment and on rising edge of sensor_2 it should decrement
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 process(clock) begin if rising_edge(clock) then if ((Q1 = '1') and (Q2 = '0')) then -- Anything here will only be executed on precisely one clock cycle which corresponds to -- the time of the rising edge of 'sensor_1' elsif (....) -- Think you can figure out how to do the same type of thing with sensor_2 --- Anything here will only be executed on precisely one clock cycle which corresponds to -- the time of the rising edge of 'sensor_2' end if; end if; end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 entity visitor_counter is Port ( --sys_clk : in STD_LOGIC; sensor_1 : in STD_LOGIC ; sensor_2 : in STD_LOGIC ; rst : in STD_LOGIC; -- H : out STD_LOGIC_vector(3 downto 0); T : out STD_LOGIC_vector(3 downto 0); O : out STD_LOGIC_vector(3 downto 0)); end visitor_counter; architecture Behavioral of visitor_counter is -- signal clk1 : std_logic; -- signal visitor_count : integer :=0; signal ones, tens : integer :=0; -- signal hundreds : integer :=0; signal sensor_1_prev, sensor_2_prev : std_logic :='0'; -- COMPONENT clk_div -- PORT( -- sys_clk : IN std_logic; -- q : OUT std_logic -- ); -- END COMPONENT; begin -- Inst_clk_div: clk_div PORT MAP( -- sys_clk => sys_clk, -- q => clk1 -- ); process (rst, sensor_1, sensor_2) begin if rst='1' then ones<= 0; tens<= 0; -- hundreds<= 0; end if; if sensor_1='1' and sensor_1_prev='0' then ones <= ones + 1 ; -- if ones>9 then -- tens<=tens+1; -- ones<=0; -- if tens>9 then -- hundreds<=hundreds+1; -- tens<=0; -- end if; -- end if; sensor_1_prev<='1'; elsif sensor_1='0' then sensor_1_prev<='0'; end if; if sensor_2='1' and sensor_2_prev='0' then ones <= ones - 1 ; -- if ones<0 then -- tens<=tens-1; -- ones<=9; -- if tens<0 then -- hundreds<=hundreds-1; -- tens<=9; -- end if; -- end if; sensor_2_prev<='1'; elsif sensor_2='0' then sensor_2_prev<='0'; end if; --else -- --ones <= ones; --tens <= tens; --hundreds <= hundreds; --end if; --case hundreds is --when 0 => -- H<="0000"; --when 1 => -- H<="0001"; --when 2 => -- H<="0010"; --when 3 => -- H<="0011"; --when 4 => -- H<="0100"; --when 5 => -- H<="0101"; --when 6 => -- H<="0110"; --when 7 => -- H<="0111"; --when 8 => -- H<="1000"; --when others => -- H<="1001"; -- hundreds <=0; --end case; case tens is when 0 => T<="0000"; when 1 => T<="0001"; when 2 => T<="0010"; when 3 => T<="0011"; when 4 => T<="0100"; when 5 => T<="0101"; when 6 => T<="0110"; when 7 => T<="0111"; when 8 => T<="1000"; when 9 => T<="1001"; when 10 => -- hundreds<=hundreds+1; tens <=0; when others => -- hundreds<=hundreds-1; tens <=9; end case; case ones is when 0 => O<="0000"; when 1 => O<="0001"; when 2 => O<="0010"; when 3 => O<="0011"; when 4 => O<="0100"; when 5 => O<="0101"; when 6 => O<="0110"; when 7 => O<="0111"; when 8 => O<="1000"; when 9 => O<="1001"; when 10 => tens<=tens+1; ones <=0; when others => tens<=tens-1; ones <=9; end case; end process; end Behavioral;
You didn't follow most of my suggestions, including he most important.This is what I have done after reading your suggestions.
Code VHDL - [expand] 1 process(clock)
Code VHDL - [expand] 1 process (rst, sensor_1, sensor_2)
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 process(clock) begin if rising_edge(clock) then if ((Q1 = '1') and (Q2 = '0')) then -- Anything here will only be executed on precisely one clock cycle which corresponds to -- the time of the rising edge of 'sensor_1' elsif (....) -- Think you can figure out how to do the same type of thing with sensor_2 --- Anything here will only be executed on precisely one clock cycle which corresponds to -- the time of the rising edge of 'sensor_2' end if; end if; end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 process (rst, sensor_1, sensor_2) begin if rst='1' then -- Stuff end if; if sensor_1='1' and sensor_1_prev='0' then -- Stuff sensor_1_prev<='1'; elsif sensor_1='0' then sensor_1_prev<='0'; end if; if sensor_2='1' and sensor_2_prev='0' then -- Stuff sensor_2_prev<='1'; elsif sensor_2='0' then sensor_2_prev<='0'; end if; end process;
Code VHDL - [expand] 1 if sensor_1='1' and sensor_1_prev='0' then
Code VHDL - [expand] 1 if sensor_1_prev='1' and sensor_1_prev_2='0' then
The way to answer the question about whether it serves your purpose and whether changes need to be made is through simulation and perusal of the synthesis warnings that came out that you ignored. To be blunt though, 'no', what you have will not work.It has removed the error but will it serve my purpose? Is there any need for making any change in it?
Code VHDL - [expand] 1 2 3 4 5 if rising_edge(clock) then if (Rst = '1') then -- Stuff elsif ((Q1 = '1') and (Q2 = '0')) then ... (as shown in previous post)
entity visitor_counter is
Port ( sys_clk : in STD_LOGIC;
sensor_1 : in STD_LOGIC ;
sensor_2 : in STD_LOGIC ;
rst : in STD_LOGIC;
-- H : out STD_LOGIC_vector(3 downto 0);
T : out STD_LOGIC_vector(3 downto 0);
O : out STD_LOGIC_vector(3 downto 0));
end visitor_counter;
architecture Behavioral of visitor_counter is
signal clk1 : std_logic;
-- signal visitor_count : integer :=0;
signal ones, tens : integer :=0;
-- signal hundreds : integer :=0;
signal sensor_1_prev_1, sensor_1_prev_2, sensor_2_prev_1, sensor_2_prev_2 : std_logic :='0';
COMPONENT clk_div
PORT(
sys_clk : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
begin
Inst_clk_div: clk_div PORT MAP(
sys_clk => sys_clk,
q => clk1
);
process (clk1)
begin
if rising_edge(clk1) then
sensor_1_prev_1<=sensor_1;
sensor_1_prev_2<=sensor_1_prev_1;
sensor_2_prev_1<=sensor_2;
sensor_2_prev_2<=sensor_2_prev_1;
if rst='1' then
ones<= 0;
tens<= 0;
-- hundreds<= 0;
elsif (sensor_1_prev_1='1') and (sensor_1_prev_2='0') then
ones <= ones + 1 ;
if ones>9 then
tens<=tens+1;
ones<=0;
-- if tens>9 then
-- hundreds<=hundreds+1;
-- tens<=0;
-- end if;
end if;
elsif (sensor_2_prev_1='1') and (sensor_2_prev_2='0') then
ones <= ones - 1 ;
if ones<0 then
tens<=tens-1;
ones<=9;
-- if tens<0 then
-- hundreds<=hundreds-1;
-- tens<=9;
-- end if;
end if;
end if;
--else
--
--ones <= ones;
--tens <= tens;
--hundreds <= hundreds;
end if;
end process;
process (ones, tens)
begin
case ones is
when 0 =>
O<="0000";
when 1 =>
O<="0001";
when 2 =>
O<="0010";
when 3 =>
O<="0011";
when 4 =>
O<="0100";
when 5 =>
O<="0101";
when 6 =>
O<="0110";
when 7 =>
O<="0111";
when 8 =>
O<="1000";
when others =>
O<="1001";
end case;
case tens is
when 0 =>
T<="0000";
when 1 =>
T<="0001";
when 2 =>
T<="0010";
when 3 =>
T<="0011";
when 4 =>
T<="0100";
when 5 =>
T<="0101";
when 6 =>
T<="0110";
when 7 =>
T<="0111";
when 8 =>
T<="1000";
when others =>
T<="1001";
end case;
--case hundreds is
--when 0 =>
-- H<="0000";
--when 1 =>
-- H<="0001";
--when 2 =>
-- H<="0010";
--when 3 =>
-- H<="0011";
--when 4 =>
-- H<="0100";
--when 5 =>
-- H<="0101";
--when 6 =>
-- H<="0110";
--when 7 =>
-- H<="0111";
--when 8 =>
-- H<="1000";
--when others =>
-- H<="1001";
-- hundreds <=0;
--end case;
end process;
end Behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 library ieee; use ieee.std_logic_1164.all; entity tb_visitor_counter is end tb_visitor_counter; architecture RTL of tb_visitor_counter is signal sys_clk: STD_LOGIC := '0'; signal sensor_1: STD_LOGIC ; signal sensor_2: STD_LOGIC ; signal rst: STD_LOGIC; signal T: STD_LOGIC_vector(3 downto 0); signal O: STD_LOGIC_vector(3 downto 0); signal Sim_Complete: std_ulogic := '0'; signal My_Count: integer := 0; type t_Test_Phase is (Reseting, Test_Sensor_1, Test_Sensor_2, Test_Simultaneous, No_Counting, Count_Once); signal Test_Phase: t_Test_Phase; begin sys_clk <= not(Sim_Complete) and not(sys_clk) after 10 ns; rst <= '1', '0' after 30 ns; MAIN : process begin Test_Phase <= Reseting; sensor_1 <= '0'; sensor_2 <= '0'; wait until (rst = '0') and rising_edge(sys_clk); report "Generate some rising edges on sensor_1"; Test_Phase <= Test_Sensor_1; for i in 1 to 100 loop sensor_1 <= '1'; wait until rising_edge(sys_clk);sensor_1 <= '0'; wait until rising_edge(sys_clk); end loop; wait until rising_edge(sys_clk); wait until rising_edge(sys_clk); wait until rising_edge(sys_clk); wait until rising_edge(sys_clk); report "Should have counted up 100 times at this point...does it cause the counter to wrap around?"; Test_Phase <= Test_Sensor_2; for j in 1 to 100 loop sensor_2 <= '1'; wait until rising_edge(sys_clk);sensor_2 <= '0'; wait until rising_edge(sys_clk); end loop; report "Should have counted back down to 0 at this point...did it?"; Test_Phase <= Test_Simultaneous; report "Now let's test to see that the counter does not count when it shouldn't with simultaneous edges on sensor_1 and sensor_2"; for i in 1 to 10 loop sensor_1 <= '1'; sensor_2 <= '1'; wait until rising_edge(sys_clk); sensor_1 <= '0'; sensor_2 <= '0'; wait until rising_edge(sys_clk); end loop; Test_Phase <= No_Counting; report "Now let's test to see that the counter does not count when it shouldn't with sensor_1 and sensor_2 always 0"; sensor_1 <= '0'; sensor_2 <= '0'; for i in 1 to 10 loop wait until rising_edge(sys_clk); wait until rising_edge(sys_clk); end loop; Test_Phase <= Count_Once; report "Now let's test to see that the counter does not count more than once when it shouldn't with sensor_1 and sensor_2 always 1"; sensor_1 <= '1'; sensor_2 <= '1'; for i in 1 to 10 loop wait until rising_edge(sys_clk); wait until rising_edge(sys_clk); end loop; Sim_Complete <= '1'; report "Simulation complete"; wait; end process; process begin wait until rising_edge(sensor_1) or rising_edge(sensor_2) or rising_edge(Sim_Complete); if (Sim_Complete = '0') then if rising_edge(sensor_1) then if not(rising_edge(sensor_2)) then My_Count <= My_count + 1; end if; elsif rising_edge(sensor_2) then My_Count <= My_count - 1; end if; end if; end process; DUT : entity work.visitor_counter Port map( sys_clk => sys_clk, sensor_1 => sensor_1, sensor_2 => sensor_2, rst => rst, T => T, O => O); end RTL;
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