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Pls explain the principle of this circuit in details

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samuel

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Object: want to transfer some charge from STORE PMOS to Cap.

I just know that it is analog shift register similar 3 phase CCD structure, but i dont kow how it perform this task. Anyone can tell me how it works.

Thankyou very much

Control Sequece as attachment control sequence files.

Circuit as attachment circuit schematic.
 

eda_freak

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read the book on MOS transistor and circuit design by kang...it has details about such structure...i.e.. how much every node charges by bcoz for MOS to conduct Vgs>Vt...apply this idea and u'l reach 2 da answer..
 

    samuel

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samuel

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thanks,eda_freak.

where to find this book you mentioned?
 

unkarc

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samuel said:
thanks,eda_freak.

where to find this book you mentioned?
Maybe you could ask for it in a university or technical library.

There exists an inter-library service too when you may get a book in 1-2 weeks' time so your local library may also of help.

rgds
unkarc
 

samuel

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MOS transistor and circuit design by kang.


Anyone can introduce this book in details?
 

beckchm

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where can download this book
 

Vamsi Mocherla

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This circuit should conduct a perfect '1' and a bad '0'. Hence the output will be VDD when all the inputs are high and VTH above GND when the inputs will be zero. The rest of it is all timing information. The VTH of the which device is determined by the input timing information.

Added after 2 minutes:

Oh I am sorry that I did not notice the NMOS device. But the logic to be looked into is that PMOS is a bad conductor of zero and a good conductor of one and the opposite is the case for the NMOS.
 

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