Pll transfer function model based on verilogA

[alpacinoliu]

How to see the total phsase noise at synthesizer output?

Here is my method.

freely run every block:

PFD+CHarge_Pump+filter in locking condition ----pss to save the output noise

saved in V.^2/Hz


VCO----pss to save phase noise in DB20

10.^(DB20/10)*4

divider----same

crystal----same



using noise source in new schematic to represent above noise source.

and create verilogA block to represent transfer function from noise to output,


and

AC+Noise

then you will see total ,

please minus 20log(4) from the result DB20

 

[edajason]

Would you mind posting a template of your verilogA code? If no IP involved.

Thanks

How to see the total phsase noise at synthesizer output?

Here is my method.

freely run every block:

PFD+CHarge_Pump+filter in locking condition ----pss to save the output noise

saved in V.^2/Hz


VCO----pss to save phase noise in DB20

10.^(DB20/10)*4

divider----same

crystal----same



using noise source in new schematic to represent above noise source.

and create verilogA block to represent transfer function from noise to output,


and

AC+Noise

then you will see total ,

please minus 20log(4) from the result DB20