wccheng
Full Member level 5
Dear all,
I am simulating transient of the PLL in schematic view. However, it is so strange to me. Firstly, I have designed the QVCO. It would oscillate 4GHz at 0.9V Vctrl voltage. I have included the output loading when I design the QVCO. Afterwards, I do the whole PLL simulation result. It finds that the Vctrl = 0.7V in order to get stable. However, my partner using the same circuit and run the simulation in another PC. It gives Vctrl = 0.85V in order to get stable. Why does it happen? Do I need to set something in the simulation in order to get a consistent solution?
Thanks
wccheng
I am simulating transient of the PLL in schematic view. However, it is so strange to me. Firstly, I have designed the QVCO. It would oscillate 4GHz at 0.9V Vctrl voltage. I have included the output loading when I design the QVCO. Afterwards, I do the whole PLL simulation result. It finds that the Vctrl = 0.7V in order to get stable. However, my partner using the same circuit and run the simulation in another PC. It gives Vctrl = 0.85V in order to get stable. Why does it happen? Do I need to set something in the simulation in order to get a consistent solution?
Thanks
wccheng