PLL simulation problem

[wccheng]

Dear all,

I am simulating transient of the PLL in schematic view. However, it is so strange to me. Firstly, I have designed the QVCO. It would oscillate 4GHz at 0.9V Vctrl voltage. I have included the output loading when I design the QVCO. Afterwards, I do the whole PLL simulation result. It finds that the Vctrl = 0.7V in order to get stable. However, my partner using the same circuit and run the simulation in another PC. It gives Vctrl = 0.85V in order to get stable. Why does it happen? Do I need to set something in the simulation in order to get a consistent solution?

Thanks

wccheng

 

[tlihu]

Same netlists? Same model parameter? Any difference? OS? Please gives more details.

 

[wccheng]

all are same

Added after 3 hours 6 minutes:

Will transisent time step affect the simulation result in the whole PLL simulation?

 

[LvW]

Will transisent time step affect the simulation result in the whole PLL simulation?

Of course, it will - at least if the time step is above a certain limit.
Another question: What do you mean with "get stable" ???
Does this mean the loop has locked ?