Hi all,
Please help me finding a respose to this question.
In practicle the output frequency of a VCO is a function of the value of the controlling voltage input Vc. If we assume that the VCO power Supply is 3 V and taht it should be between 1V and 2 V. Suppose that the output frequency of the VCO is supposed to be maintained at f_o. This means that I have to maintain the voltage Vc (which is the output of the charge pump circuit) stable. ( let say at 1.5 V ).
We know that, if Vc increase f decrease and Vice versa.
My question is
When we have f=f_o then we must have Vc=1.5 which is not the case since the output of the Charge pump in such situation is zero.
In other word, how to design circuit that:
- decreases Vc when f<f_o
- increase Vc when f>f_o
- Maintain Vc=1.5V if f=f_o ?
I know solution that use the Amp op in order to perform the comparaison task but I'm looking for the most simple circuit responding to my question.
as the PLL start , the two input are not the same , specially the VCO will start in the free running , then the feedback action will begin to develop the voltage on the Vcrtl and then the loop willbe stable , so the voltage will still as required
Please take a look to the document that I sent you in PM. My problem is that when 0<Vc<1 V or 2<Vc<3V the VCO output is not a periodic sine, not stable and the signal is very weak.
In my case, your last reply becames valid only if we garantee that Vc is always between 1 and 2 V.
Yes.
Note that in my PLL I didn't represent the sine to Square converter (a 2 stage of inverter between the VCO and the freq divider). Transient simulation shows a random curves (for exemple for Vc=350 mV starting from 65 ns in the simulation).