PLL: Regarding Charge pump

[master_picengineer]

pll reverso

Hi all,
Please help me finding a respose to this question.
In practicle the output frequency of a VCO is a function of the value of the controlling voltage input Vc. If we assume that the VCO power Supply is 3 V and taht it should be between 1V and 2 V. Suppose that the output frequency of the VCO is supposed to be maintained at f_o. This means that I have to maintain the voltage Vc (which is the output of the charge pump circuit) stable. ( let say at 1.5 V ).
We know that, if Vc increase f decrease and Vice versa.
My question is
When we have f=f_o then we must have Vc=1.5 which is not the case since the output of the Charge pump in such situation is zero.
In other word, how to design circuit that:
- decreases Vc when f<f_o
- increase Vc when f>f_o
- Maintain Vc=1.5V if f=f_o ?

I know solution that use the Amp op in order to perform the comparaison task but I'm looking for the most simple circuit responding to my question.

 

[khouly]

a very simple way , reverse the two input of the PFD , is is always a trick done

or reverse the output of the PFD make up used as down and down as up

khouly

 

[master_picengineer]

Hi ,
First of all, happy new year hijri 1429.
Thanks Khouly for your reply. But I think you misunderstood my question.

See, when the 2 inputs of the PFD have the same frequency and are in phase, UP and Down are zero. In ths case I like to have Vc=1.5 V.

 

[khouly]

as the PLL start , the two input are not the same , specially the VCO will start in the free running , then the feedback action will begin to develop the voltage on the Vcrtl and then the loop willbe stable , so the voltage will still as required

khouly

 

[master_picengineer]

Please take a look to the document that I sent you in PM. My problem is that when 0<Vc<1 V or 2<Vc<3V the VCO output is not a periodic sine, not stable and the signal is very weak.
In my case, your last reply becames valid only if we garantee that Vc is always between 1 and 2 V.

 

[fanshuo]

There is a steady-state error between the two input of the PFD which would make the input of the VCO to maintain 1.5V

 

[khouly]

i saw the document , the problem is when the Vc is out of the range , the VCO is not functioning proberly

u need to try transient simulation , and check the
pefromance

the output of the VCO not necessay to be sinwave , specially it will pass through divider so to will be look like didigtal pulse to the PFD

so it is ok

khouly

 

[master_picengineer]

i saw the document , the problem is when the Vc is out of the range , the VCO is not functioning proberly

u need to try transient simulation , and check the
pefromance

the output of the VCO not necessay to be sinwave , specially it will pass through divider so to will be look like didigtal pulse to the PFD

so it is ok

khouly

Yes.
Note that in my PLL I didn't represent the sine to Square converter (a 2 stage of inverter between the VCO and the freq divider). Transient simulation shows a random curves (for exemple for Vc=350 mV starting from 65 ns in the simulation).

 

[khouly]

mmm , it is strange , i think u need to modify ur VCO to work with the PLL

khouly

 

[mooner]

only simulate the VCO to check that when control voltage equals to 1.5, whether the VCO frequency could need the requiment ?