PLL REF CLOCK mod with DDS

[7rots51]

pll mod

Hello

Is it possible to FSK modulate the reference clock input of PLL synthesizer IC (for ex ADF4360) with a DDS IC(for ex AD9954) to obtain FSK modulated carrier signal?

I use a high bandwidth PLL loop filter.

 

[madengr]

dds pll

I suppose you could if you needed a DC response but most FSK demodulators are AC coupled to allow for carrier drift so you won't gain anything by doing so. Usually the modulation is AC coupled into the loop filter. Just make sure your data is "DC free" so it needs 4B5B coding or something similar to remove long strings of ones and zeros.

Many fractional-N synthesizer IC's are coming with modulation inputs so you can toggle between divisor values to FSK modulate.

Google "two point modulation" and you will get a bunch of info.

 

[biff44]

dds vco

Sure, why not!

Of course, you have to realize the nuances of such an approach:
* The phase noise of the final signal would be worse, as you in effect multiplying the DDS signal by the XN of the PLL divider
* All DDS signals have spurious outputs--an artifact of trying to make an analog signal out of a fixed bit quantized digital signal. Those RF spurious tones will also be multiplied by XN in the PLL, which would be a real trouble in a wireless applicatinon where out of band signals have to be reduced to meet a spectrum mask.
* As you allude to, the bandwidth of the PLL will alter the dynamics of the FSK modulating signal. If you are sending digital symbols, for instance, the higher the data rate, the more distortion you will have. Do not forget that even though a PLL can be said to have a "bandwidth" of say 1 MHz, there is significant phase shift of the modulating signal at even 200 KHz. There is also tansport lag in the PLL, which will look like a time delay to your FSK modulation.

 

[7rots51]

modulating the reference in pll

thanks to all

Many fractional-N synthesizer IC's are coming with modulation inputs so you can toggle between divisor values to FSK modulate.

plz give me some part number?

 

[madengr]

dds reference clock

SKY72302

**broken link removed**

 

[7rots51]

dds clock synthesizer

I have a 512kbps serial data that is manchester encoded and want to convert it to binary FSK with 3MHZ deviation,which solution is better?

DDS+Integer PLL ?

or

Fractional PLLs like as SKY72302 ?

does fractional PLLs can FSK modulate high data rates like as 512kbps or 1Mbps?

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for

All DDS signals have spurious outputs

We can use a BPF like as SAW filter at output of DDS,It will removes frequency spurs of DDS.Is this a good solution for spurs removing?

 

[biff44]

using dds as a fractional divisor in pll

Man, you're out of control. Are you a student just trying to do things in a weird way, or are you a practical engineer trying to make a usable datalink? None of your ideas make sense.

 

[7rots51]

use dds with pll

I am student and like to tst ideas and methods,

Removing spurs that is generated with a DDS ,can be removed by a band pass filter,Is this a wrong idea?

 

[biff44]

ad9958 loop filter

Good. Students should explore new ways to do things! Keep at it!

The standard way to do this is to use a very narrowband phase locked loop with a very large divisor ratio (maybe 20,000), and AC couple the digital signal onto the VCO tuning line. The narrowband loop keeps the frequency excursions "averaged" to be centered around the desired middle frequency.

For low bandwidth applications, you can actually change the divisor ratio to give two different locked frequencies (as in going from 20,000 to 20,003 for a divisor ratio). You would need a faster loop bandwidth for this.

There are other ways to do it though. You could use an image reject mixer downconverting the signal before the PLL divisor, and add, and then subtract, a pilot tone signal.

You could have a fixed frequency PLL, and send the VCO output thru a 3 bit phase shifter, and step the phase upward in uniform steps for a while (will look like a lower frequency), and then step the phase downward inuniform steps for a while (will look like a higher frequency)--serodyne phase shifting.

You could use a regenerative frequency divider and a PLL that can have more than one divisor ratio, such as divide by 3, 4,5,6 etc, and coarse tune the VCO to force a divide by 5, and then a divide by 6.

There are lots of ways to skin a cat!

 

[7rots51]

dds modulation

The standard way to do this is to use a very narrowband phase locked loop with a very large divisor ratio (maybe 20,000), and AC couple the digital signal onto the VCO tuning line. The narrowband loop keeps the frequency excursions "averaged" to be centered around the desired middle frequency.

VCOs (above 1 GHZ) have 20~50MHz /Volt sensitivity if I want to fsk modulate a TTL data with 100KHZ deviation ,I need to convert TTL signal to a 25mV p-p square wave and apply it to VCO Vtune!
This low level data signal is very noise sensitive and I do not have a stable and good modulated signal,for solving this problem I should have a 1MHZ/Volt VCO that is not available in market(a narrowband VCO),I have to designe it!

Another solution is to use quadrature modulator and a quadrature DDS,I used
AD8349 and AD9958 but AD8349 is very weak in practical use and I need a good IQ modulator with good carrier suppression,do you know any?