PLL Design with amplifier

[Dines]

We have designed PLL for operating range 11-14 GHz, Our design made output of VCO directly go to amplifier then to divider. Refer the attached picture.

Is there anything affect PLL locking time or performance because we are placing amplifier in it?

Can anyone please please clarify on this ?

 

[BigBoss]

The PLL Loop Filter is dominant on Locking Time so there won't be any problem.

 

[biff44]

nope. an RF amplifier with 4 Ghz of bandwidth will have very little group delay. AND it buffers the VCO from load variations, so it is a good thing.

however...you do realize that the DIVIDE BY N part imparts a HUGE "transport lag" in your control loop. to a first order, it adds open loop control system phase shift, which will tend to make a control loop more unstable. either it might not lock, or it will ring as it tries to lock. So you would need to compentsate that transport lag in your analog loop filter design, or at least be aware of it

For a divide by 22,134, for example, these dividers will count input cycles, say 22,134 of them, then put out ONE output pulse. So for 22,133 of those input cycles, your control loop has no clue what the VCO phase has done! Then, boom, it gets one measurement pulse, and it might over correct.

an analogy is that you are driving your car down a highway, but a friend in the back seat puts a cardboard piece in front of your eyes for 20 seconds out of every 21 seconds. can you keep the car on the road, or will your control system go unstable (and you hit the guard rail)?