PLL power supply noise rejection

Status
Not open for further replies.
E

edajason

Member level 3
Joined
Nov 5, 2004
Messages
60
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
441
When design a PLL chip, do you guys use an internal voltage regulator to provide power supply for the chip core?
For industry, people might choose this way to improve the supply noise performance. Any inputs?
 

use voltage regulator to improve the PLL's phase noise including divider,charge-pump,pfd and vco.
 

but the regulator's high frequency rejection is more critical when in noisy digital chip
 

PLL jitter minimization

how to minimize jitter in PLL using Verilog code
 

it is some help for adding the reg
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…