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Power supply sequencing question


Full Member level 3
Mar 13, 2015
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Hello all,


I am trying to implement a simple power supply sequencing that I saw on an ADI article. The picture above shows what I am trying to recreate. My timing requirements aren't strict, I simply need my positive rails turn on before any negative rail and the negative rails to turn off before the positive. So a simple RC time delay on the regulators' enable pins should be enough.
However, my situation is a bit different than the picture above. I do not have a switch to energize / de-energize the RC time delays. I have a daughter board plugging into mother board. The physical connection to the motherboard energizes or de-energizes the board. The power on sequence makes sense. However, I am not entire sure what happens when I unplug the daughter board. (Referenceing the diagram above) When the switch is opened C1 and C2 are discarged through D2, R2, D4, R4 back to the return path. In my case, when I discconect the daugter board, technicly i remove the return path for that discharge current. Am I overthinking this problem, or will removing that return path cause issues? I'm going to go try it on a bread board, but my gut is telling me that charge has no where to go.

Thanks in advance

There are dedicated power sequencing ICs. Did you check them?
And there are "hot plug" controller ICs.

Power sequencing demands can be elaborate and maybe
even over-the-top. A key question is whether anything
destructive can happen during the "quench" (discharge)

If diode currents flow forward through ESD networks and
the close-in filter caps are modest, the energy dropped
may be a "don't care". Certainly many many products take
no such pains. But the devel is in the details. What you don't
want is the core of a high-core-current FPGA left to make up
its own music after the I/O rails have gone insane-o.

If I had a victim surplus I might try lashing up the simplest
"turnon in sequence, turn off in gang" scheme I could come
up with, and abuse it until I got bored or got failure. If the
power tree is not complex then simultaneous bring-up may
be tolerable (have read some FPGA DSes which say this),
but if ramp rates are not aligned and instant, then follow the
drawn out sequence. Comes down to cases, and cases have
fine print.

Definitely look into purpose-made sequencers and any apps
schematics the FPGA vendor may have already developed,
which might point you to the one they think best for the FPGA
in question.
Thanks for the reply. Thankfully Im not dealing with a FPGA, simply some RF components: ADRF5044 (SP4T), ADRF5730 (variable attenuation). But you are 100% spot on with dumping current through the protection diodes. Espeically if you apply any of the digitial control signals before Vdd.
--- Updated ---

There are dedicated power sequencing ICs. Did you check them?
Yes. You have to imagine the ADI document ends with a pretty good advert for their power sequencing products. In the previous version of this system we ended up create some needlessly complicated digital logic circuit to control relays after power regulation. Some folks on the project didn't think it was wise to use the enable pins (they had some BS reason i didn't believe).
However, they are gone, and now its up to me. And its time to simply things. I only shy away from dedicated ICs because its not something I could test without buying eval boards or other hardware.
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from my experience:
* often it is more "safe" to use a voltage depending sequencing (using comparators) than a timing dependent sequencing
* often there are simple and rugged solutions, like a schottky power diode from +3.3V supply (anode) to +5V supply (cathode) (obvioously does not work on negative and positve supplies combined)
* I had a problem with a positive negaitve power supply using 78xx and 79xx devices. When the 78xx device was the first to power up, then the negative one got stuck at about zero volts.
This did only happen on second source 79xx devices. The solution was to place a diode across IN and OUT of the 79xx device.
* I dot like the idea to switch DC supply voltage using relays. The reason is that you usually need capacitors at both sides of the switch. This creates huge current peaks on switch ON. I rather use some "soft switching" MOSFETs. Also dedicated hot swap circuits usually care for this.

I don´t see why an IC can´t be tested without eval boards. I do this all the time.


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