dhasmana
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Hi,
When we know the loop bandwidth (depending upon the reference frequency) then how do we decide on how much R and how much C we should put?Means how do we divide the desired RC for R and C?
On what factors, the accumulated jitter of a PLL depend?What is the typical value of accumulated jitter for a PLL with output freq ~ 100MHz in say 130nm technology?
How is static phase error translated into jitter?Please comment.
Regards,
Jitendra.
When we know the loop bandwidth (depending upon the reference frequency) then how do we decide on how much R and how much C we should put?Means how do we divide the desired RC for R and C?
On what factors, the accumulated jitter of a PLL depend?What is the typical value of accumulated jitter for a PLL with output freq ~ 100MHz in say 130nm technology?
How is static phase error translated into jitter?Please comment.
Regards,
Jitendra.