pll lock problem - what caused this spur or ripple?

[mengcy]

problem with wander pll

Hi,
I met a problem when simulate the whole loop of PLL. Locking spent about 30us, but after about 80us, Vcrl(the input of VCO) exhibits a ripple about 40mV.and it seems like it will appear again after an amount of time.

my question is: what caused this spur or ripple? Is it possible that it is caused by the simulation tools (Hsim)?

The coefficients are listed below:
Kvco=50M Hz/V,
Icp=20u,
ratio=90,
Fref=4M,
the loop filter is characterized by
Rp=90kHz,
Cp=57.26p,
C1=9.7p
I calculated the loop bandwidth is about 200kHz, and I test the phase margin is 45deg.

 

[LvW]

pll low frequency ripple

It is quite normal to observe a ripple on top of the control voltage.
The main reason, normally, is the lowpass filter which has not sufficient damping for the unwanted frequency components. Therefore, some additional filtering is to be provided with a pole outside the loop bandwidth (because of loop stability).

Recommendation: Measure the frequency of the ripple and check if it is one of the unwanted frequency componenets created by the PD.
BTW: Which kind of PD are you using ?

 

[mengcy]

pll lock problem

Thanks!
The ripple occurs at a very low frequency,smaller than Fref, I wander how can the additional filter outside the loop bandwidth can suppress this kind of ripple.

PD is the most popular circuit,refer to the analog CMOS
written by Razavi.

 

[LvW]

Re: pll lock problem

Thanks!
The ripple occurs at a very low frequency,smaller than Fref, I wander how can the additional filter outside the loop bandwidth can suppress this kind of ripple.

Yes, the additional pole can resp. shall reduce only frequency components above incoming resp. reference frequency.
If the ripple frequency is "very low" this could be an indication that the loop has not locked and cannot regulate, because it is the main purpose of the PLL to reduce such low frequency variations.