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PLL : Issue in Phase Locking

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cmos_dude

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I have designed a CMOS PLL @ .15u.
I am able to get a frequency lock but there is a constant phase difference between the Input reference and the VCO o/p.
Is this because of the dead zone of the PFD or am I missing something ???

Thanks in advance
Rgds
Cmos Dude
 

mpig09

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Hi :

Maybe it is dead zone.
First,you can check the output signals of PFD (up / down) are work or not ?

Second, you can verify your PFD when you input two clock to check dead zone
range, then solve it !!!

Third, if your PFD has response, the you must to check charge pump switch is
work or not ?

mpig09
 

rfsystem

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I think deadtimes in the loop result in dynamic bang-bang behaviour of the phase and not in a static phase offset!

There could be two other reasons:

1. The loop filter has to low gain at zero frequency. That could be because there is a leakage path parallel to the integration cap for a passive loop filter. Or the opamp, in the case of an active loop filter, has to low gain.

2. The charge pump requires some phase offset to generate zero mean charge if the output voltage change from the nominal point.
 

cmos_dude

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Hi RF
The second point that you have suggested, This phase offset varies as I vary my reference input frequency.
That is, for a particular reference frequency, the phase offset has a unique value.
 

rfsystem

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You can use a chargepump with lower output conductance. That means longer, and for the same current and VDSAT greater, devices. So the chargepump current does not change much over the chargepump output voltage control range. The disadvantage that is become slower.
 

montage2000

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there is a lot of reasons , deadzone, charge injection, clock feedthrough and skew of UP/DN
all can induce it , check these.

Added after 10 minutes:

balance everything in two clock path
 

hanjiemy

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yes,
1. check deadzone.
2. check mismatch and leakage of source/sink.
3. are u sure it's locked? loop isn't unstable?
4. I think PLL need this small phase different keep it in "locking".
 

cmos_dude

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hanjiemy said:
yes,
1. check deadzone.
2. check mismatch and leakage of source/sink.
3. are u sure it's locked? loop isn't unstable?
4. I think PLL need this small phase different keep it in "locking".
Yes I am sure that it is locked as the phase difference remains constant throughout the simulation, moreover the frequency of oscillation of the VCO output is exactly double that of the input (I have used a TFF to obtain a duty cycle of 50%, which the VCO O/P was not giving)
and i did not understand what you mean by " I think PLL need this small phase different keep it in "locking" Please elaborate.

Rgds
Cmos Dude
 

kamalakkannan

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hi,,

i have a diff way of answer for this.

assume u have opamp with 60db openloop gain.now you use this opamp in unity gain buffer mode and give 1v to positive pin of opamp..idealy you are suppose to get 1v at o/p..but u get 999m only..diff b/w inputs of opamp is 1mv(static volatage diff)...this is becuase of finite open loop gain of opamp.if u want to reduce this,u have to increase the AV of opamp.
similarly in PLL,instead of voltage,you will get constant phase diff at pll input even after pll is locked.this static phase error phase error will give spurious tones(=near ref input freq)..so if u want to reduce this error,then u may have to increase the gain of ur pll.
hope it helps you..

--
kamal.
 

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