pll feed sequence in lpc2148 arm controller

[iec.naga@ymail.com]

pll feed sequence is always 0xaa followed by 0x55. why is it so. what is the format of pllfeed register in lpc2148. how to configure it.

 

[mathespbe]

Not only for PLL. It's common for WDT as well. To configure a system peripheral which involves the clock directly, needs this feed sequence...

 

[Venkadesh_M]

pll feed sequence is always 0xaa followed by 0x55. why is it so. what is the format of pllfeed register in lpc2148. how to configure it.

There is No format for feed register when toggling all its bits it starts PLL..

0xAA 10101010
0x55 01010101

sample code

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Code C - [expand]
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void PLL_init(void)
{
  PLLCFG   = 0x00080016;   // configure
  PLLCON   = 0x00000003;   // enable
  PLLFEED  = 0x000000AA;   // feed
  PLLFEED  = 0x00000055;
}

---

 

[mathespbe]

pll feed sequence is always 0xaa followed by 0x55. why is it so. what is the format of pllfeed register in lpc2148. how to configure it.

void PLL_Init(void)
{
PLL0CON = 0x01;
PLL0CFG = -----; //Calculate the multiplier and divide value from thye formulas==>
/*The PLL output frequency (when the PLL is both active and connected) is given by: CCLK = M x FOSC or CCLK = FCCO / (2 x P)
The CCO frequency can be computed as:FCCO = CCLK x 2 x P or FCCO = FOSC x M x 2 x P*/

PLL0FEED = 0xAA;
PLL0FEED = 0x55;

}

This might be the proper configuration setup for PLL...

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There is No format for feed register when toggling all its bits it starts PLL..

0xAA 10101010
0x55 01010101

[/syntax]

why do we need to give these values by consecutive clock cycles? If you say it's just to toggle the bits, you can also give the sequence in the reverse order too? Why it doesn't work when you change the sequence?

Can you please explain me?

 

[Venkadesh_M]

why do we need to give these values by consecutive clock cycles? If you say it's just to toggle the bits, you can also give the sequence in the reverse order too? Why it doesn't work when you change the sequence?

Can you please explain me?

Yeah, That is its architecture thats why we are doing....

 

[iec.naga@ymail.com]

Yeah, That is its architecture thats why we are doing....

Dear Venkadeshm..
thanks for your reply. but i would like to know the architecture of pllfeed sequence. . .

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Dear Sir

may i know y only this feed sequence is required. but i am really thankful for your answer sir.

 

[Venkadesh_M]

Dear Venkadeshm..
thanks for your reply. but i would like to know the architecture of pllfeed sequence. . .

Hi naga,
There is no architecture for pllfeed,Its just a way we are doing, I talked about ARM7 architecture.

 

[embpic]

means by givving sequence of 0x55 and 0xaa it toggles bit so in 1 instruction cycle it toggles 8-times. and which is given to our system clock source.
Is it right?

 

[mathespbe]

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Dear Sir

may i know y only this feed sequence is required. but i am really thankful for your answer sir.

I's just a security check to enable system clock of ARM controller...
The unique security sequence is 0xAA and 0x55... These values are just consider as a magic words...

there is nothing meaning behind this feed sequence...
To make the changes in your system clock you just ned this sequence to feed...