Re: PLL: Cycle slipping detector, lock detection, please hel
Reply from safwatonline,
Hello wylee,
i dont have too much information about the lock detector except the basic operation, but here is what i think anyway:
the cycle slipping seems to be good and simple way to detect the lock but it has a main disadvantage that u cannot accuratly detect the lock as in some application like in CDR u need to get the lock detection in terms of UI and switch to the phase allignment loop acording to this value (and vice versa), but on the other hand it makes a really simple solution for non-accurate detection, if u want an accurate detection i suggest the counter methode.
anyway to be exactly sure , there is an obvious solution which is making a large signal model \"using verilog-A for instance\" and do some simulations , this must be done anyway \"i guess\" during the PLL design and if u choosed to do the Cycle slipping Lock Detector then as u can see it is nothing more than the extra to FF\'s which u should have already made in ur model.
sorry that i couldn\'t help any more .
regards