PLL Bandwidth Phase margin and Jitter

[mouzid]

pll bandwidth and jitter

Hello Edaboarders,

How to choose the bandwidth/phase margin to make the Jitter as small as possible ?

Thanks.

 

[saro_k_82]

bandwidth phase margin

To minimize the jitter, one needs to minimize the phase noise at the output.
The VCO noise is high pass filtered while the open loop VCO noise itself falls at 20 or 30dB per decade. The noise from PFD-CP, Reference and the dividers are low pass filtered. So the choice of BW must be such that at that frequency the contribution from the VCO is equal to the contribution from PFD-CP, reference and the dividers.
The LPF R noise is bandpass filtered, but it is too low to be considered in most applications.