[SOLVED] Please verify the 2 bit counter design using JK flip flop

[sri4ever]

Hello,

I'm new to VHDL. I have designed the 2 bit up counter using JK flip flop. But the test bench is not producing the results i need.
Please find attached the vhdl code and the test bench.

--- 2 bit counter with JK FF

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counterusingJK is
Port ( --JK: in std_logic_vector ( 1 downto 0) :="11";
CLK : in STD_LOGIC := '1';
RST : in STD_LOGIC := '0';

Qout : out STD_LOGIC_VECTOR(1 downto 0)
);
end counterusingJK;

architecture Behavioral of counterusingJK is
signal Q : std_logic_vector(1 downto 0);
signal JA,JB,KB : std_logic :='1';
signal KA : std_logic;
signal QA :std_logic := '1' ;
signal QB : std_logic := '1';

begin
KA <= QB;
--Q <= QA&QB;
process (CLK,RST)
begin
if (RST = '1') then
Q <= "00";

elsif (CLK ='1') then

Q <= (QA&QB)+1;
end if;

end process;
Qout <= Q;

end Behavioral;

-------------------------------------------------------------------------------------

Test Bench for 2 bit counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY UPcounter IS
END UPcounter;

ARCHITECTURE behavior OF UPcounter IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT counterusingJK
PORT(
CLK : IN std_logic;
RST : IN std_logic;
Qout : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;


--Inputs
signal CLK : std_logic := '0' ;
signal RST : std_logic := '0';


--Outputs
signal Qout : std_logic_vector(1 downto 0) ;

-- Clock period definitions
constant CLK_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: counterusingJK PORT MAP (

CLK => CLK,
RST => RST,
Qout => Qout
);

-- Clock process definitions
CLK_process rocess
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;


-- Stimulus process
stim_proc: process
begin
--wait for clk_period*20;
RST <= '1';
--CLK <= '1';
-- hold reset state for 100 ns.
wait for 10 ns;

-- wait for CLK_period*10;
RST <= '0';
--CLK <= '1';
wait for 10 ns;

-- insert stimulus here

wait;
end process;

END;




Kindly suggest where could be the mistake.
Thanks,
Sri

 

[TrickyDicky]

first of all, you commented out the J and K inputs!

 

[sri4ever]

first of all, you commented out the J and K inputs!

Thanks for your reply. But the two JK flip flops are internal to the circuit. Hence I have declared them internally. Considering a black box circuit, only clk and reset are the inputs with Qout as the output.

---------- Post added at 17:30 ---------- Previous post was at 15:47 ----------

Thanks for your reply. But the two JK flip flops are internal to the circuit. Hence I have declared them internally. Considering a black box circuit, only clk and reset are the inputs with Qout as the output.

I was able to resolve it..
thanks

 

[asi2k7]

5 bit gray counter needed

Hi
i need to design a 5 bit Sync. Gray UP Counter using JK -Flip Flop
any help or circuit of MultiSim
Please Help
i have seen 3-Bit counter in Thomas .L Floyd book
thanks in advanced