Please verify-circuit after output in an IC

[circuitking]

Hi, I have connected the below circuit to include the bond wire inductance, pad capacitance, transmission lines and ESD circuit. I would like to have a discussion on whether I have to improve it. Outputs of LVDS driver are given as inputs to circuitry.

1. This is how my ESD circuit looks like. Is it just enough or are there anythings to consider in ESD circuit?
**broken link removed**

2. For bond-pad capacitance I used 2 pF capacitors.
3.I took, randomly, 5 mm Bond-wire-so inductance of 5 nH and 250 mohm resistance assuming gold bond-wire. I have no idea how to take the coupling between the two wires, so I just gave K= 0.1
4. As we don't have package I didn't include its capacitance.
5.I just kept Tline for channel with below parameters. It provides only delay. please tell me how to include channel behavior here.

6. Am I missing any other components? how does this whole circuitry impact the LVDS driver design. Thanks

 

[dick_freebird]

2pF is excessive for a regular bond pad.
You could calculate a more reasonable
value from technology information in the
PDK modeling documents.

Your ESD clamp is probably worthless. At
least half of it is (the GGPMOS will not snap
back usefully and will likely self destruct if
it's got to take ESD current at breakdown
voltage). The GGNMOS could suffice if
properly designed (silicide block extent,
metallization) and sized (Vsnapback@Iesd).

Wirebond inductance is about 1nH/mm,
a 5mm bond wire is pretty long in an open
cavity or CoB; don't know what plastic
packaging allows.

 

[circuitking]

Wirebond inductance is about 1nH/mm,
a 5mm bond wire is pretty long in an open
cavity or CoB; don't know what plastic
packaging allows.

Can you comment anything on the mutual inductance between the wires?.
What about channel modelling: Tline?