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PLEASE HELP!!!vhdl code 4 bit sync conter t flip flop structure

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tonnes9

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hello every1 i am kind of a newbie to vhdl design.how do i design a 4 bit synchronous counter which uses T type flip flop?the counter increments on each positive edge of the clock if enable signal is asserted.
the counter is reset to 0 by using reset signal.
it uses an AND gate,where Tn=Q0Q1.....Qn-1

since its a synch. counter does it matter i use a synchr. reset or asynchr. reset?pls help realy urgent!!!
 
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lucbra

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synchronous counter has nothing to do with synchronous reset or async reset

Just google and you will find numerous examples.
 

tonnes9

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thanx lucbra for d reply i jus got a code but i am not so sure if it a synch. or asynch counter could any1 help me verify?stating why it is for either case??thanx

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY sync_counter IS
port (clock, Resetn, E : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END sync_counter;

ARCHITECTURE Behavior OF sync_counter IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF REsetn = '0' THEN
Count <= "0000" ;
ELSIF (Clock'EVENT AND Clock = '1')THEN
IF E = '1' THEN
Count <= Count + 1;
ELSE
Count <= Count;
END IF;
END IF;
END PROCESS;
Q <= Count;
END Behavior;
 

TrickyDicky

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its a synchronous counter because all of the counting occurs on clock edges.
 

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