sharkya2a
Junior Member level 1
FPGA vertex 5
hi all
I'm new here ( with computer science background )
I've FPGA vertex 5 110T with ISE 11.1
i tried to deal with it but i faced some problems.
i built my code using VHDL, it works fine
The Synthesizing for the VHDL code was done correctly using Xilinx ISE 11.1
The Programming File was generated.
The program file was programmed on the FPGA by iMPACT tool.
The Communication between the FPGA and PC using the HyperTerminal (sending an input data and receiving an output data) was done
just for the demo code which was exist on the Compact Flash.
i have some questions:
should i use the EDK for my project or i can directly programed the bit-file which is resulted from the ISE ?
How can I determine the input and output for the FPGA ?
may you will find that my questions are very simple or trivial, as I said to you earlier "I'm new here with computer science background".
So my experience in dealing with FPGA's is very weak.
I tried to do my best, I have read many articles and explanations, especially from Xilinx website but I could not find the specific answers that I want.
Dealing with the FPGA's is a big and comples topic and Xilinx website very larg, therefore it contains a lot of interventions which led to my inability to get accurate information that I need.
So I'll be grateful for any advice or recommendation
best regards
hi all
I'm new here ( with computer science background )
I've FPGA vertex 5 110T with ISE 11.1
i tried to deal with it but i faced some problems.
i built my code using VHDL, it works fine
The Synthesizing for the VHDL code was done correctly using Xilinx ISE 11.1
The Programming File was generated.
The program file was programmed on the FPGA by iMPACT tool.
The Communication between the FPGA and PC using the HyperTerminal (sending an input data and receiving an output data) was done
just for the demo code which was exist on the Compact Flash.
i have some questions:
should i use the EDK for my project or i can directly programed the bit-file which is resulted from the ISE ?
How can I determine the input and output for the FPGA ?
may you will find that my questions are very simple or trivial, as I said to you earlier "I'm new here with computer science background".
So my experience in dealing with FPGA's is very weak.
I tried to do my best, I have read many articles and explanations, especially from Xilinx website but I could not find the specific answers that I want.
Dealing with the FPGA's is a big and comples topic and Xilinx website very larg, therefore it contains a lot of interventions which led to my inability to get accurate information that I need.
So I'll be grateful for any advice or recommendation
best regards
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