Please help urgent !!Regarding post route simulation

[arunjatti]

hi all,

I'm running a post route simulation, but i hve glitches in my output , how to recover from it ,please help its urgent

 

[echo47]

Add registers to your output signals.

Some glitches are harmless.

If that doesn't help you, then give more information.

 

[arunjatti]

Hi echo,

Thankyou very much, i got it

 

[badaseshi]

Hello I have glitches in the out put of my post route simulation. Behavioural simulation output is correct. But post route simulation output is wrong.

Here is a register called data_reg_in which is asynchronously updated. It ia assigned to data_reg_out signal on pos edge of the clock cycle. data_reg_out is assigned to output port.


WITH data_reg_mux_sel SELECT
data_reg_in <= round0_out WHEN "00",
round1_10_out WHEN "01",
X"00112233445566778899aabbccddeeff" WHEN OTHERS;
PROCESS(clk, load_data_reg, data_reg_in) -- RESET WAS HERE!!!!!
BEGIN

IF(clk'event AND clk='1') THEN
IF(load_data_reg='1') THEN
data_reg_out <= data_reg_in;
END IF;
END IF;
END PROCESS;

Can you please propose a solution?