Please help to write VHDL code of following counter

[naavid]

Can you please help me to write VHDL program for the ones-counting state machine as described by the following state table

C D Q QN
1 0 0 1
1 1 1 0
0 X last Q last QN

Many thanks,

 

[K-J]

Can you please help me to write VHDL program for the ones-counting state machine as described by the following state table

C D Q QN
1 0 0 1
1 1 1 0
0 X last Q last QN

Many thanks,

Post what you've done so far and where you're having trouble...otherwise you might give people the impression that you're too lazy to do your own work.

Kevin

 

[naavid]

Please tell me where i am wrong......

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_counter is
port (
coutQ ut std_logic_vector (1 downto 0); -- Q Output of the counter
coutQN ut std_logic_vector (1 downto 0); -- QN Output of the counter
enable :in std_logic; -- Enable counting
clk :in std_logic; -- Input clock
reset :in std_logic -- Input reset
);
end entity;

architecture rtl of up_counter is
signal count :std_logic_vector (1 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
count <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
count <= count + 1;
elsif (enable = '0') then
count <= count;
end if;
end if;
end process;
coutQ <= count;
coutQN <= not count;
end architecture;