Please help!!!! Time back annotated simulation design step by step guide

tariq786 said:

You need sdf file (standard delay format) file which can be obtained by running static timing analysis on the design using Synopsys Primetime tool or doing synthesis of the design using Synopsys Design Compiler. Once you have sdf file. You can run it on the synthesized gate level netlist by putting the following in your test bench file

initial
begin
$sdf_annotate("filename.sdf",top_level_instance_name); //for example $sdf_annotate("./design/gate_level/vga_enh_top_ps.sdf",test.UUT)
end

This will do the back annotated timing simulation

Hope this helps

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tariq786 said:

Please try cadence encounter tool

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