Please help me with the project in USB transmitter

Similar threads

• S

  HELP ME WITH THIS ISSUE PLEASE. IT'S URGENT.

  • Started by Soh_bhat
  • Apr 1, 2023
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• D

  [SOLVED] VHDL code bug in sim - please help me

  • Started by daniel bet
  • Feb 17, 2023
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• K

  What's the difference between RAM and ROM with a coe files in Xilinx FPGA?

  • Started by kevinwang65
  • Mar 11, 2024
  • Replies: 13

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  [SOLVED] Please help for Data transferring between Verilog Modules

  • Started by EDA_hg81
  • Aug 12, 2023
  • Replies: 0

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  How can I run verilog code with data at a specific time in the past?

  • Started by alexis57
  • Jan 28, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design