please help me to fix my translation from VHDL to Verilog

Kushanku · Nov 13, 2013

Hello, i tried to translate from myself these 3 file from VHDL to Verilog.
I post the VHDL first and then mine translation. Can you help me to check it and fix it?

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
ENTITY VGA IS
PORT(
CLOCK_24: IN STD_LOGIC_VECTOR(1 downto 0);
VGA_HS,VGA_VS: OUT STD_LOGIC;
VGA_R,VGA_G,VGA_B: OUT STD_LOGIC_VECTOR(3 downto 0);
KEY: IN STD_LOGIC_VECTOR(3 downto 0);
SW : IN STD_LOGIC_VECTOR(1 downto 0)
);
END VGA;
 
 
 
 
ARCHITECTURE MAIN OF VGA IS
 
SIGNAL VGACLK,RESET: STD_LOGIC:='0';
---------------------------------------------
    component PLL is
        port (
            clk_in_clk  : in  std_logic := 'X'; -- clk
            reset_reset : in  std_logic := 'X'; -- reset
            clk_out_clk : out std_logic         -- clk
        );
     end component PLL;
--------------------------------------------
COMPONENT SYNC IS
PORT(
CLK: IN STD_LOGIC;
HSYNC,VSYNC: OUT STD_LOGIC;
R,G,B : OUT STD_LOGIC_VECTOR(3 downto 0);
KEYS: IN STD_LOGIC_VECTOR(3 downto 0);
S: IN STD_LOGIC_VECTOR(1 downto 0)
);
END COMPONENT SYNC;
BEGIN
C1: SYNC PORT MAP(VGACLK,VGA_HS,VGA_VS,VGA_R,VGA_G,VGA_B,KEY,SW);
C2: PLL PORT MAP(CLOCK_24(0),RESET,VGACLK);
 
 
END MAIN;

Code Verilog - [expand]
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module VGA(clock_24, vga_hs, vga_vs, vga_r, vga_g, vga_b, key, sw);
input [1:0] clock_24;
input [1:0] sw;
input [3:0] key;
output [3:0] vga_r;
output [3:0] vga_g;
output [3:0] vga_b;
 
wire vga_hs, vga_vs;
wire [3:0] vga_r, vga_g, vga_b;
wire vgaclk =1'bz; 
reg reset;
initial reset =1'b0:
 
//-----------------------------------
        //PLL
//-----------------------------------
 
 
SYNC c1(.clk(vgaclk), .hsync(vga_hs), .vsync(vga_vs), .r(vga_r), .g(vga_g), .b(vga_b), .keys(key), .s(sw));
PLL c2(.clk_in_clk(clock_24[0]), .reset_reset(reset), .clk_out_clk(vgaclk));
endmodule

the next two VHDL codes are converted in one Verilog code (because verilog doesn't use PACKAGE, so i created a TASK in verilog to include it)

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
PACKAGE MY IS
PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos: IN INTEGER;SIGNAL RGB:OUT STD_LOGIC_VECTOR(3 downto 0);SIGNAL DRAW: OUT STD_LOGIC);
END MY;
 
PACKAGE BODY MY IS
PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos: IN INTEGER;SIGNAL RGB:OUT STD_LOGIC_VECTOR(3 downto 0);SIGNAL DRAW: OUT STD_LOGIC) IS
BEGIN
IF(Xcur>Xpos AND Xcur<(Xpos+100) AND Ycur>Ypos AND Ycur<(Ypos+100))THEN
  RGB<="1111";
  DRAW<='1';
  ELSE
  DRAW<='0';
END IF;
END SQ;
END MY;

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my.all;
 
 
ENTITY SYNC IS
PORT(
CLK: IN STD_LOGIC;
HSYNC,VSYNC: OUT STD_LOGIC;
R,G,B : OUT STD_LOGIC_VECTOR(3 downto 0);
KEYS: IN STD_LOGIC_VECTOR(3 downto 0);
S: IN STD_LOGIC_VECTOR(1 downto 0)
);
END SYNC;
 
 
ARCHITECTURE MAIN OF SYNC IS
SIGNAL RGB: STD_LOGIC_VECTOR(3 downto 0);
SIGNAL DRAW1,DRAW2: STD_LOGIC;
SIGNAL SQ_X1,SQ_Y1: INTEGER RANGE 0 TO 1688:=600;
SIGNAL SQ_X2,SQ_Y2: INTEGER RANGE 0 TO 1688:=500;
SIGNAL HPOS: INTEGER RANGE 0 TO 1688:=0;
SIGNAL VPOS: INTEGER RANGE 0 TO 1066:=0;
BEGIN
SQ(HPOS,VPOS,SQ_X1,SQ_Y1,RGB,DRAW1);
SQ(HPOS,VPOS,SQ_X2,SQ_Y2,RGB,DRAW2);
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
    IF(DRAW1='1')THEN
        IF(S(0)='1')THEN
         R<=(OTHERS=>'1');
         G<=(OTHERS=>'0');
         B<=(OTHERS=>'0');
       ELSE
         R<=(OTHERS=>'1');
        G<=(OTHERS=>'1');
        B<=(OTHERS=>'1');
       END IF;
    END IF;
    IF(DRAW2='1')THEN
        IF(S(1)='1')THEN
         R<=(OTHERS=>'1');
         G<=(OTHERS=>'0');
         B<=(OTHERS=>'0');
       ELSE
         R<=(OTHERS=>'1');
       G<=(OTHERS=>'1');
        B<=(OTHERS=>'1');
       END IF;
    END IF;
    IF(DRAW1='0' AND DRAW2='0')THEN
       R<=(OTHERS=>'0');
      G<=(OTHERS=>'0');
       B<=(OTHERS=>'0');
    END IF;
  IF(HPOS<1688)THEN
  HPOS<=HPOS+1;
  ELSE
  HPOS<=0;
      IF(VPOS<1066)THEN
          VPOS<=VPOS+1;
          ELSE
           IF(S(0)='1')THEN
              IF(KEYS(0)='0')THEN
              SQ_X1<=SQ_X1+5;
              END IF;
              IF(KEYS(1)='0')THEN
              SQ_X1<=SQ_X1-5;
              END IF;
              IF(KEYS(2)='0')THEN
              SQ_Y1<=SQ_Y1+5;
              END IF;
              IF(KEYS(3)='0')THEN
              SQ_Y1<=SQ_Y1-5;
              END IF;
            END IF;
           IF(S(1)='1')THEN
              IF(KEYS(0)='0')THEN
              SQ_X2<=SQ_X2+5;
              END IF;
              IF(KEYS(1)='0')THEN
              SQ_X2<=SQ_X2-5;
              END IF;
              IF(KEYS(2)='0')THEN
              SQ_Y2<=SQ_Y2+5;
              END IF;
              IF(KEYS(3)='0')THEN
              SQ_Y2<=SQ_Y2-5;
              END IF;
            END IF;  
          VPOS<=0;
      END IF;
  END IF;
  IF(HPOS>48 AND HPOS<160)THEN
     HSYNC<='0';
      ELSE
      HSYNC<='1';
  END IF;
  IF(VPOS>0 AND VPOS<4)THEN
    VSYNC<='0';
     ELSE
     VSYNC<='1';
  END IF;
  IF((HPOS>0 AND HPOS<408)OR(VPOS>0 AND VPOS<42))THEN
  R<=(OTHERS=>'0');
  G<=(OTHERS=>'0');
  B<=(OTHERS=>'0');
  END IF;
END IF;
END PROCESS;
END MAIN;

now the Verilog version of SYNC + MY

Code Verilog - [expand]
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module SYNC(clk, hsync, vsync, r, g, b, keys, s);
input clk;
output hsync, vsync;
output [3:0] r, g, b;
input [3:0] keys;
input [1:0] s;
 
wire hsync, vsync;
wire [3:0] r, g, b;
 
wire [3:0] rgb;
wire draw1, draw2;
wire [10:0] sq_x1, sq_y1, sq_x2, sq_y2;
wire [10:0] hpos, vpos;
sq(hpos, vpos, sq_x1, sq_y1, rgb, draw1);
sq(hpos, vpos, sq_x2, sq_y2, rgb, draw2)
:
 
always @ (posedge clk) begin
    if (draw1==1) begin
        if (s(0)==1) begin
            r <= 'b 1;
            g <= 'b 0;
            b <= 'b 0;
        end else 
        begin
            r <= 'b 1;
            g <= 'b 1;
            b <= 'b 1;
        end
    end
    if (draw2==1) begin
        if (s(1)==1) begin
            r <= 'b 1;
            g <= 'b 0;
            b <= 'b 0:
        end else 
        begin
            r <= 'b 1;
            g <= 'b 1;
            b <= 'b 1;
        end
    end
    if (draw1==0 && draw2==0) begin
        r <= 'b 0;
        g <= 'b 0;
        b <= 'b 0;
    end
    if (hpos < 1688) begin
        hpos <= hpos+1;
    end else 
    begin
        hpos <= 0;
        if (vpos < 1066) begin
            vpos <= vpos+1;
        end else
        begin 
            if (s(0)==1) begin
                if (keys(0)==0) begin
                    sq_x1 <= sq_x1+5;
                end
                if (keys(1)==0) begin
                    sq_x1 <= sq_x1-5;
                end
                if (keys(2)==0) begin
                    sq_y1 <= sq_y1+5;
                end
                if (keys(3)==0) begin
                    sq_y1 <= sq_y1-5;
                end
            end
            if (s(1)==1) begin
                if (keys(0)==0) begin
                    sq_x2 <= sq_x2+5;
                end
                if (keys(1)==0) begin
                    sq_x2 <= sq_x2-5;
                end
                if (keys(2)==0) begin
                    sq_y2 <= sq_y2+5;
                end
                if (keys(3)==0) begin
                    sq_y2 <= sq_y2-5;
                end
            end
            vpos <= 0;
        end     
    end
    if (hpos>48 && hpos<160) begin
        hsync<=0;
    end else 
    begin
        hsync<=1;
    end
    if (vpos>0 && vpos<4) begin
        vsync <= 0;
    end else 
    begin
        vsync <= 1;
    end
    if ((hpos>0 && hpos<408) || (vpos>0 && vpos<42)) begin
        r <= 'b 0;
        g <= 'b 0;
        b <= 'b 0;
    end
end
 
task sq;
    input xcur;   
    integer xcur;
    input ycur;
    integer ycur;
    input xpos;
    integer xpos;
    input ypos;
    integer ypos;   
    output [3:0] rgb;
    reg [3:0] rgb;
    output draw;
    reg draw;
    begin
        if (xcur > xpos && xcur < (xpos + 100) && ycur > ypos && ycur < (ypos + 100)) begin
            RGB = 4'b1111;
            DRAW = 1'b1;
        end else
        begin
            DRAW = 1'b0;
        end
    end
endtask
 
endmodule

thank you to everyone will help me
regards

soloktanjung · Nov 14, 2013

Hi,

I think,one way to check it is by simulating the VHDL code and then compared with the output of translated Verilog using the same testbench architecture.

Thanks

Kushanku · Nov 18, 2013

soloktanjung said:
Hi,

I think,one way to check it is by simulating the VHDL code and then compared with the output of translated Verilog using the same testbench architecture.

Thanks

i'll try soon as possible, thank you very much for your answer

Welcome to EDAboard.com

please help me to fix my translation from VHDL to Verilog

Kushanku

Newbie level 2

soloktanjung

Full Member level 6

Kushanku

Newbie level 2

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