please help me some Quizs in syntax VHDL ?

-----Quiz 1
Determine whether the relational operation is syntactically correct. If yes, what
is the result (i.e., true or false)?
(a) "0110" > “1001”
(b) "0110" > "000"
(c) 2#1010# > "1010"
(d) 1010 > "1010"

case1 : assume that the data type is unsigned
case2 : assume that the data type is signed

-----Quiz 2
Determine whether the following signal assignment is syntactically correct. If not,
use the proper conversion function and type casting to correct the problem.

library ieee ;
use ieee.std_logic_1164. all ;
use ieee.numeric_std. all ;

signal s1, s2, s3, 94, s5, s6, s7: std_logic_vector(3 downto 0);
signal u1, u2, u3, u4, u5, u6, u7: unsigned(3 downto 0);
signal sg: signed(3 downto 0) ;

U1 <= 2#0001#;
u2 <= u3 and u4;
U5 <= s1 + 1;
u6 <= u3 + u4 + 3;
u7 <= (others=>'1');
s2 <= s3 + s4 -1;
s5 <= (others=>'1');
s6 <= u3 and u4;
sg <= u3 - 1;
s7 <= not sg;

------------ thanks ---------

sounds like homework to me.

My mind has suddenly gone blank.....

exactly

hey,

Why dont you try.. and post your views.. on these questions.. so that we can help you..

Posting questions like this is not a good way to learn.

Thanks for providing the brain teaser! I thought I knew the answer to all the quiz questions except for the ones with expressions like 2#0001# in it. So thanks to your lazy homework I googled it and found out how based literals work in vhdl, thanks! So now I think I know all the answers for this quiz. w00t! progress!

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verylsi said:

Posting questions like this is not a good way to learn.

Click to expand...

Turns out that in a convoluted way it was. Just not for him.

thanks ! please check for me :
--------
Quiz 1 :

+ case data type is unsigned :

a. "0110" > "1001" : syntax correct , result : false ( 6 > 9)
b. "0110" > "0001001" : syntax correct , result : false ( 6 > 9)
c. 2#1010# > "1010" : ? ( i dont know)
d. 1010 > "1010" : ? ( i dont know)

+ case data type signed :

a. "0110" > "1001" : syntax correct , result : true ( 6 > -7)
b. "0110" > "0001001" : syntax correct , result : false ( 6 > 9)
c. 2#1010# > "1010" : ? ( i dont know)
d. 1010 > "1010" : ? ( i dont know)

--------------
Quiz2 :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......

signal s1, s2, s3, s4, s5, s6, s7: std_logic_vector(3 downto 0);
signal u1, u2, u3, u4, u5, u6, u7: unsigned(3 downto 0);
signal sg: signed(3 downto 0) ;

......

U1 <= 2#0001#; -- error -- edited : U1 <= to_unsigned (2#0001#,4);
u2 <= u3 and u4; -- correct
U5 <= s1 + 1; -- error -- edited : U5 <= unsigned(s1) + 1;
u6 <= u3 + u4 + 3; -- correct
u7 <= (others=>'1'); -- correct
s2 <= s3 + s4 -1; -- error -- edited : s2 <= std_logic_vector(unsigned (s3) + unsigned (s4) -1);
s5 <= (others=>'1'); -- correct
s6 <= u3 and u4 ; -- error -- edited : s6 <= std_logic_vector(u3 and u4);
sg <= u3 - 1; -- error -- edited : sg <= signed(u3) - 1;
s7 <= not sg; -- error -- edited : s7 <= not std_logic_vector(sg);

-----------------
please help me check answers and complete miss .

For c) google on "vhdl based literals". And with a bit of luck you'll read about literals in general which magically solves d) for you as well.

mrflibble said:

For c) google on "vhdl based literals". And with a bit of luck you'll read about literals in general which magically solves d) for you as well.

Click to expand...

+ case data type is unsigned :
c. 2#1010# > "1010" : syntax correct : result : false ( 10 > 10 )
d. 1010 > "1010" : error

+ case data type signed :

c. 2#1010# > "1010" : syntax correct : result true ( 10 > -6)
d. 1010 > "1010" : error

-- are these right ?

1010 is just an integer (one thousand and ten), and you can compare an integer to a signed/unsigned.

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PS. Hurray for a lecturer who uses numeric_std. I never thought Id see the day.

TrickyDicky said:

1010 is just an integer (one thousand and ten), and you can compare an integer to a signed/unsigned.

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PS. Hurray for a lecturer who uses numeric_std. I never thought Id see the day.

Click to expand...

So, there is no error in Quiz 1 ?????

I think 1.d is syntactically correct, so then your answer of "error" would be in error.

PS. Hurray for a lecturer who uses numeric_std. I never thought Id see the day.[/QUOTE]

Hello Tricky.. I have a question regarding the use of numeric_std.all, I don't know why its not recommended, may be because it needs type conversion , or its not recommended because of portability issues of the code... I really don't know.

But I use it at times when I need to do operation on both unsigned and signed data types, and its easier to do the conversion, than fighting with the ambiguities of std_logic_signed.all package and std_logic_unsigned.ll package..

What should be the right thing to do? and why is numeric_std package not recommended?
Thanks for your help in advance...

numeric_std IS recommended. And it is also an IEEE standard.

Thanks tricky.. sorry I misunderstood your comment...