Please Help! LVS check error

[hubo8918]

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Hi, I run the LVS check it says"source primary cell "RCA" not found in source database". The RCA is my library and top cell name. The schematic is import from verilog netlist file using verilogin. Then export hspice netlist using the ADE L.
Thanks in advance

 

[tariq786]

It seems like an info message not a warning!

How does schematic look like? Is RCA in the schematic or it is broken down into individual gates? Post the picture of rca schematic. Also post the picture of rca layout. Compare the two. layout should match schematic. If not, see if any switches are turned on to do schematic to layout optimization.

 

[hubo8918]

I add the .subckt of the RCA cell and solve the problem. However, it gives me a new error, which says "noting in layout".