"Please check your core height setting" Error when Creating Floorplan In IC Compiler

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ryu_hayabusa

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"Please check your core height setting" Error when Creating Floorplan In IC Compiler

Hi, I keep getting this error when creating floorplan in ICC:

------------------------------------------------------------------------------
icc_shell> create_floorplan -start_first_row -flip_first_row -left_io2core 5 -bottom_io2core 5 -right_io2core 5 -top_io2core 5
0 pads are constrained in TDF table
There are 3 IO pads 0 corner pads in total
Number of Rows = 0. Please check your core height setting.
------------------------------------------------------------------------------

Have anyone encounter this error before in ICC? How to fix this?
 

Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi


your core area is empty, zero rows. do you have any std cells in your design?
 

Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi

Thanks for your reply, my design has std cells. This is the netlist I used. It is actually a PWM signal generator, synthesized using Design Compiler:

Code: 
-------------------------------------------
module Top_PWM_Gen ( Clk, Rst, PWM_Out );
  input Clk, Rst;
  output PWM_Out;
  wire   Clk_, Rst_, U_PWM_WW_N16, U_PWM_WW_N15, U_PWM_WW_N14, U_PWM_C_N1, n8,
         n9, n10, n11;
  wire   [6:4] U_PWM_WW_Out;

  PIC U_Clk ( .IE(1'b1), .P(Clk), .Y(Clk_) );
  PIC U_Rst ( .IE(1'b1), .P(Rst), .Y(Rst_) );
  POC2A U_PWM_Out ( .A(U_PWM_C_N1), .P(PWM_Out) );
  DFFHQX1 U_PWM_WW_counter_WW_reg_4_ ( .D(U_PWM_WW_N14), .CK(Clk_), .Q(
        U_PWM_WW_Out[4]) );
  DFFHQX1 U_PWM_WW_counter_WW_reg_5_ ( .D(U_PWM_WW_N15), .CK(Clk_), .Q(
        U_PWM_WW_Out[5]) );
  DFFHQX1 U_PWM_WW_counter_WW_reg_6_ ( .D(U_PWM_WW_N16), .CK(Clk_), .Q(
        U_PWM_WW_Out[6]) );
  NOR2XL U17 ( .A(U_PWM_WW_Out[4]), .B(Rst_), .Y(U_PWM_WW_N14) );
  NAND2XL U18 ( .A(U_PWM_WW_Out[5]), .B(U_PWM_WW_Out[4]), .Y(n11) );
  OAI21XL U19 ( .A0(U_PWM_WW_Out[5]), .A1(U_PWM_WW_Out[4]), .B0(n11), .Y(n8)
         );
  NOR2XL U20 ( .A(Rst_), .B(n8), .Y(U_PWM_WW_N15) );
  NAND3XL U21 ( .A(U_PWM_WW_Out[5]), .B(U_PWM_WW_Out[4]), .C(U_PWM_WW_Out[6]), 
        .Y(U_PWM_C_N1) );
  INVXL U23 ( .A(U_PWM_WW_Out[6]), .Y(n10) );
  INVXL U24 ( .A(U_PWM_C_N1), .Y(n9) );
  AOI211XL U25 ( .A0(n11), .A1(n10), .B0(Rst_), .C0(n9), .Y(U_PWM_WW_N16) );
endmodule

----------------------------------

I am using the same reference library in ICC as in DC. But still I have problem creating the floorplan.
 
Last edited by a moderator:

Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi

I think I found out the issue already. It seems that the IO pad cells are larger than the core area. This is due to the IO pad cells lib file is different with the std cells lib file. Can we adjust the core height & width manually?

 

Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi


Yes, of course you can. Check the floorplanning options. I am not sure this is your problem, as IO cells are not supposed to live in the core area.
 

Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi

Thanks again for your opinion. I have run the "check_library" command to check the libraries, and here's the output:



Is it normal for standard cells lib & IO cells lib having the different tile size? For the milkyway lib's tile size, is it always be the same as the stand cells' tile size?
 

Re: "Please check your core height setting" Error when Creating Floorplan In IC Compi

Of course it is normal, IO cells are huge. They can be 100x bigger than a standard cell, easily.
 

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