edk tool plb
You should read the documents from the EDK DOC folder. specially, if you are developing an IP and wanted to attached to the Xilinx FPGA system, then read est_rm.pdf. Also read plb_usage.pdf, which will give you idea about the standard interface required for PLB bus in FPGA. Then you need to remember to use some of the IP's from EDK like "proc_common", "plbv46_slave_single or burst", "interrupt_controller" like IP's where number of ready references are available for address decoding, data aligning, interrupt handling etc. Then you should design files like .mpd, .pao, .tcl(optional) so that your IP can be "fit" in EDK requirement. If you complete this, then you have achieved almost half the mile stone. After doing this, you can check if your IP is suitable for EDK environment, by starting a new "dummy" build using BSB of EDK. Remember to keep your core (it should be like core_name_ver_00_a) in local PCORE directory. Once your base build is completed, then just copy any of the IP instances in MHS and modified that instance with your core name, parameter settings and dont do any address manipulation here. Once you complete insertion of your core in MHS, then use "Auto Address GEneration" technique of EDK tool. If it gives error like, " the core is not attached to PLB", then thought "Bus Interface" tab of "System Assembly View", click on the core name and attached your core to any of the buses available as slave. This will attach your core to PLB and then do address generation. If at this moment the addresses are generated properly, then it means that your core is attached to PLB and recognized by the EDK tool. Later comes the software part. I will explain this part later once you reach till this level.