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Platform Studio and the EDK tools ?

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khamitkar.ravikant

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mbmpsoc

please anybody can explain me what are EDK tools
which components are included in these tools
how i can use that tools to implement cryptogrphic alogorithms
please somebody help?

i will be thankful to u

please
 

xilinx edk pcore interrupt

will it be possible to design any cryptographic system using the edk tools with help of Microblaze.
please let me know if possible i want to work out things on that
 

xilinx edk create bsb problem

please check also this link, it maybe very useful for you, as i see it has C source code of the algorithm!

**broken link removed**
 
edk plb cores

hi there
i have started working on implementation of AES on xilinx ISE tool with a VHDL.
so i will need your co operation time to time
i expect u will help me in that
thanks alot for u r information too.
 

local pcore

hi..

edk tool is callled embedded devolepment kit in which you can create you system and the peripherals.
for eg - a microblaze(processor) can be created with the perpherals like uart,memory controllers and also you can upload the software code along with your peripherals.this can be done with sdk(software devolepment kit)

you can go to xilinx site for more info

**broken link removed**
 
est_rm.pdf

You can use EDK and Platform studio to design an embedded system with the MicroBlaze CPU and a few peripherals... SDRAM, UART, Ethernet...Then use this setup to perform encryption/decryption.. To make the hardware work you will need to write C code that will initialize the CPU and peripherals and then do the encryption or decryption.
 
edk tool plb

You should read the documents from the EDK DOC folder. specially, if you are developing an IP and wanted to attached to the Xilinx FPGA system, then read est_rm.pdf. Also read plb_usage.pdf, which will give you idea about the standard interface required for PLB bus in FPGA. Then you need to remember to use some of the IP's from EDK like "proc_common", "plbv46_slave_single or burst", "interrupt_controller" like IP's where number of ready references are available for address decoding, data aligning, interrupt handling etc. Then you should design files like .mpd, .pao, .tcl(optional) so that your IP can be "fit" in EDK requirement. If you complete this, then you have achieved almost half the mile stone. After doing this, you can check if your IP is suitable for EDK environment, by starting a new "dummy" build using BSB of EDK. Remember to keep your core (it should be like core_name_ver_00_a) in local PCORE directory. Once your base build is completed, then just copy any of the IP instances in MHS and modified that instance with your core name, parameter settings and dont do any address manipulation here. Once you complete insertion of your core in MHS, then use "Auto Address GEneration" technique of EDK tool. If it gives error like, " the core is not attached to PLB", then thought "Bus Interface" tab of "System Assembly View", click on the core name and attached your core to any of the buses available as slave. This will attach your core to PLB and then do address generation. If at this moment the addresses are generated properly, then it means that your core is attached to PLB and recognized by the EDK tool. Later comes the software part. I will explain this part later once you reach till this level.
 
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