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pipelining 32 float point adder design

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jerryhqp

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float adder

i am designing a 32bit pipelining float point adder design,I have finished it and test it,it can work at 60.5M,I hope that it can be over 100M,some body can give me some device and reference,thanks.
my email:jerryhqp@sohu.com
 

Which FPGA and tools are you using?

What do you mean by "some device and reference"?
 

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