MjWasHere
Newbie level 2
I want to implement Radix-2 Single-path Delay Feedback (SDF) Decimation-In-Frequency FFT with Pipelining in VHDL and I am trying to understand the below architecture as described in this MIT OpenCourseWare Lecture
![radix2_sdf.png radix2_sdf.png](https://www.edaboard.com/data/attachments/62/62106-612fbec8c8db5d74f8a53fd181859353.jpg)
Since its a DIF FFT, shouldn't the upper half of the data be directly passed on to the next stage without requiring multiplication with twiddle factor? Is there a multiplexer which controls multiplication and not shown in the diagram? Can anyone please elaborate on this architecture or provide other references which would help understand SDF better?
![radix2_sdf.png radix2_sdf.png](https://www.edaboard.com/data/attachments/62/62106-612fbec8c8db5d74f8a53fd181859353.jpg)
Since its a DIF FFT, shouldn't the upper half of the data be directly passed on to the next stage without requiring multiplication with twiddle factor? Is there a multiplexer which controls multiplication and not shown in the diagram? Can anyone please elaborate on this architecture or provide other references which would help understand SDF better?
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