MjWasHere
Newbie level 2
I want to implement Radix-2 Single-path Delay Feedback (SDF) Decimation-In-Frequency FFT with Pipelining in VHDL and I am trying to understand the below architecture as described in this MIT OpenCourseWare Lecture
Since its a DIF FFT, shouldn't the upper half of the data be directly passed on to the next stage without requiring multiplication with twiddle factor? Is there a multiplexer which controls multiplication and not shown in the diagram? Can anyone please elaborate on this architecture or provide other references which would help understand SDF better?
Since its a DIF FFT, shouldn't the upper half of the data be directly passed on to the next stage without requiring multiplication with twiddle factor? Is there a multiplexer which controls multiplication and not shown in the diagram? Can anyone please elaborate on this architecture or provide other references which would help understand SDF better?
Last edited: