Pipeline ADC:Problems about different results with different simulation times?

[guanglei]

I am simulating 8 bit pipeline ADC with verilog A model, sampling frequency is 16k.When I ran the transient simulation with a input ramp, the first time I choose simulation time 1/16k*512=32ms, the output is correct; the second time I doubled the simulation time and keep everything the same but result is wrong. I don't know why the result changed because of the different simulation time,anyone can give me some idea,thanks!




Guanglei

 

[crutschow]

What is "wrong" about the second result?

 

[guanglei]

I am attaching the second result of the following ideal 8 bit DAC，thanks!

 

[crutschow]

Are you referring to the spikes on the waveform as being wrong? Those may be real and they were just too fast to show up in the first simulation.

 

[guanglei]

I am attaching the two simulation results:32ms and 64ms.you can see for the 32ms simulation, the pulse step increases monotonically; but for 64ms simulation, the output is even not steps,thanks!

 

[crutschow]

There's no vertical scale shown. Are they the same for both simulations?

 

[guanglei]

Yes,they are the same vertical scale.